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[ARM64_DYNAREC] Small change on defered flag handling to make sure it…
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@ptitSeb
ptitSeb committed Jan 31, 2025
1 parent 09e0797 commit bb653e6
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Showing 3 changed files with 67 additions and 78 deletions.
36 changes: 18 additions & 18 deletions src/dynarec/arm64/dynarec_arm64_emit_logic.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ void emit_or32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3,
MAYUSE(s2);
IFX(X_PEND) {
SET_DF(s4, rex.w?d_or64:d_or32);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
ORRxw_REG(s1, s1, s2);
Expand Down Expand Up @@ -81,7 +81,7 @@ void emit_or32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int
}
IFX(X_PEND) {
SET_DF(s4, rex.w?d_or64:d_or32);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
ORRxw_mask(s1, s1, (mask>>12)&1, mask&0x3F, (mask>>6)&0x3F);
Expand Down Expand Up @@ -130,7 +130,7 @@ void emit_xor32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
MAYUSE(s2);
IFX(X_PEND) {
SET_DF(s4, rex.w?d_xor64:d_xor32);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
EORxw_REG(s1, s1, s2);
Expand Down Expand Up @@ -184,7 +184,7 @@ void emit_xor32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
}
IFX(X_PEND) {
SET_DF(s4, rex.w?d_xor64:d_xor32);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
if(!mask) {
Expand Down Expand Up @@ -237,7 +237,7 @@ void emit_and32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
MAYUSE(s2);
IFX(X_PEND) {
SET_DF(s4, rex.w?d_and64:d_and32);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_ZF|X_SF|X_CF|X_OF) {
Expand Down Expand Up @@ -289,7 +289,7 @@ void emit_and32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
}
IFX(X_PEND) {
SET_DF(s4, rex.w?d_and64:d_and32);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_ZF|X_SF|X_CF|X_OF) {
Expand Down Expand Up @@ -336,7 +336,7 @@ void emit_or8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
MAYUSE(s2);
IFX(X_PEND) {
SET_DF(s4, d_or8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
ORRw_REG(s1, s1, s2);
Expand Down Expand Up @@ -364,7 +364,7 @@ void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4)
}
IFX(X_PEND) {
SET_DF(s4, d_or8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
ORRw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
Expand All @@ -387,7 +387,7 @@ void emit_xor8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
MAYUSE(s2);
IFX(X_PEND) {
SET_DF(s4, d_xor8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
EORx_REG(s1, s1, s2);
Expand Down Expand Up @@ -415,7 +415,7 @@ void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
}
IFX(X_PEND) {
SET_DF(s4, d_xor8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
EORw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
Expand All @@ -438,7 +438,7 @@ void emit_and8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
MAYUSE(s2);
IFX(X_PEND) {
SET_DF(s4, d_and8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_ZF) {
Expand Down Expand Up @@ -483,7 +483,7 @@ void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
}
IFX(X_PEND) {
SET_DF(s4, d_and8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_ZF) {
Expand Down Expand Up @@ -523,7 +523,7 @@ void emit_or16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
MAYUSE(s2);
IFX(X_PEND) {
SET_DF(s4, d_or16);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
ORRw_REG(s1, s1, s2);
Expand Down Expand Up @@ -551,7 +551,7 @@ void emit_or16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s4
}
IFX(X_PEND) {
SET_DF(s4, d_or16);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
ORRw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
Expand All @@ -574,7 +574,7 @@ void emit_xor16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
MAYUSE(s2);
IFX(X_PEND) {
SET_DF(s4, d_xor16);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
EORw_REG(s1, s1, s2);
Expand Down Expand Up @@ -602,7 +602,7 @@ void emit_xor16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s
}
IFX(X_PEND) {
SET_DF(s4, d_xor16);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
EORw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
Expand All @@ -626,7 +626,7 @@ void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
MAYUSE(s2);
IFX(X_PEND) {
SET_DF(s4, d_and16);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_ZF) {
Expand Down Expand Up @@ -671,7 +671,7 @@ void emit_and16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s
}
IFX(X_PEND) {
SET_DF(s4, d_and16);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_ZF) {
Expand Down
38 changes: 19 additions & 19 deletions src/dynarec/arm64/dynarec_arm64_emit_math.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ void emit_add32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, rex.w?d_add64:d_add32b);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_AF) {
Expand Down Expand Up @@ -98,7 +98,7 @@ void emit_add32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRxw_U12(s5, xEmu, offsetof(x64emu_t, op2));
SET_DF(s4, rex.w?d_add64:d_add32b);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_AF) {
Expand Down Expand Up @@ -166,7 +166,7 @@ void emit_sub32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, rex.w?d_sub64:d_sub32);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_AF) {
Expand Down Expand Up @@ -238,7 +238,7 @@ void emit_sub32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
MOV64xw(s5, c);
STRxw_U12(s5, xEmu, offsetof(x64emu_t, op2));
SET_DF(s4, rex.w?d_sub64:d_sub32);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_AF) {
Expand Down Expand Up @@ -309,7 +309,7 @@ void emit_add8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, d_add8b);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_AF | X_OF) {
Expand Down Expand Up @@ -375,7 +375,7 @@ void emit_add8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRB_U12(s4, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, d_add8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_AF | X_OF) {
Expand Down Expand Up @@ -418,7 +418,7 @@ void emit_sub8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, d_sub8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_AF|X_OF|X_CF) {
Expand Down Expand Up @@ -465,7 +465,7 @@ void emit_sub8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4
STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRB_U12(s5, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, d_sub8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_AF|X_OF|X_CF) {
Expand Down Expand Up @@ -512,7 +512,7 @@ void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, d_add16b);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_AF) {
Expand Down Expand Up @@ -645,7 +645,7 @@ void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, d_sub16);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_AF|X_OF|X_CF) {
Expand Down Expand Up @@ -988,7 +988,7 @@ void emit_adc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, rex.w?d_adc64:d_adc32b);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFNATIVE_BEFORE(NF_CF) {
Expand Down Expand Up @@ -1131,7 +1131,7 @@ void emit_adc8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, d_adc8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFNATIVE_BEFORE(NF_CF) {
Expand Down Expand Up @@ -1195,7 +1195,7 @@ void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, d_adc16);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFNATIVE_BEFORE(NF_CF) {
Expand Down Expand Up @@ -1318,7 +1318,7 @@ void emit_sbb32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, rex.w?d_sbb64:d_sbb32);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFNATIVE_BEFORE(NF_CF) {
Expand Down Expand Up @@ -1467,7 +1467,7 @@ void emit_sbb8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, d_sbb8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFNATIVE_BEFORE(NF_CF) {
Expand Down Expand Up @@ -1532,7 +1532,7 @@ void emit_sbb16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
SET_DF(s3, d_sbb16);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFNATIVE_BEFORE(NF_CF) {
Expand Down Expand Up @@ -1654,7 +1654,7 @@ void emit_neg32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
IFX(X_PEND) {
STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
SET_DF(s3, rex.w?d_neg64:d_neg32);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_CF) {
Expand Down Expand Up @@ -1707,7 +1707,7 @@ void emit_neg16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
IFX(X_PEND) {
STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
SET_DF(s3, d_neg16);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_CF) {
Expand Down Expand Up @@ -1756,7 +1756,7 @@ void emit_neg8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
IFX(X_PEND) {
STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
SET_DF(s3, d_neg8);
} else IFX(X_ALL) {
} else {
SET_DFNONE();
}
IFX(X_CF) {
Expand Down
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