Fist FlooNoC integration.

Bender.lock

@@ -99,8 +99,8 @@ packages:
     dependencies:
     - common_cells
   axi_vga:
-    revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084
-    version: 0.1.3
+    revision: 4d3e70d4f47bb74edc1ab68d99ffc02382e0fb9e
+    version: 0.1.4
     source:
       Git: https://github.com/pulp-platform/axi_vga.git
     dependencies:
@@ -235,6 +235,17 @@ packages:
       Git: https://github.com/pulp-platform/event_unit_flex.git
     dependencies:
     - common_cells
+  floo_noc:
+    revision: a1241c0bce20c33504e1cffdb89fed630ee6a514
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/FlooNoC.git
+    dependencies:
+    - axi
+    - axi_riscv_atomics
+    - common_cells
+    - common_verification
+    - idma
   fpnew:
     revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315
     version: null
@@ -461,8 +472,8 @@ packages:
     - register_interface
     - tech_cells_generic
   register_interface:
-    revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
-    version: 0.4.4
+    revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467
+    version: 0.4.5
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:

Bender.yml

@@ -28,6 +28,7 @@ dependencies:
   common_cells:       { git: https://github.com/pulp-platform/common_cells.git,         version: 1.37.0                               } # branch: master        
   pulp-ethernet:      { git: https://github.com/pulp-platform/pulp-ethernet.git,        rev: 2bea11658d2bc368ae2af0a3f71b4253ba4f713f } # branch: handshake
   riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg.git,            version: =0.8.0                               }
+  floo_noc:           { git: https://github.com/pulp-platform/FlooNoC.git,              rev: a1241c0bce20c33504e1cffdb89fed630ee6a514 } # branch: yt/test
 
 workspace:
   package_links:
@@ -40,6 +41,10 @@ workspace:
 sources:
   # Configurations
     # "Small" Astral configuration
+  - target: astral_noc
+    files:
+      - hw/configs/astral_noc.sv
+
   - target: carfield_l2dual_secure_pulp_periph_can
     files:
       - hw/configs/carfield_l2dual_secure_pulp_periph_can.sv
@@ -92,6 +97,7 @@ sources:
   - hw/hyperbus_wrap.sv
   - hw/l2_wrap.sv
   - hw/ethernet_wrap.sv
+  - hw/noc_wrap.sv
   - hw/carfield_rstgen.sv
   # Level 2
   - hw/carfield.sv

bender-common.mk

@@ -6,7 +6,7 @@
 # Author: Matteo Perotti <[email protected]>
 
 # Runtime-selectable Carfield configuration
-CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can
+CARFIELD_CONFIG ?= astral_noc
 
 # bender targets
 common_targs += -t cva6

hw/carfield_pkg.sv

@@ -32,6 +32,7 @@ typedef struct packed {
 } islands_properties_t;
 
 typedef struct packed {
+  islands_properties_t cheshire;
   islands_properties_t l2_port0;
   islands_properties_t l2_port1;
   islands_properties_t safed;
@@ -40,6 +41,7 @@ typedef struct packed {
   islands_properties_t spatz;
   islands_properties_t pulp;
   islands_properties_t secured;
+  islands_properties_t dram;
   islands_properties_t mbox;
 } islands_cfg_t;
 
@@ -62,6 +64,7 @@ typedef struct packed {
   byte_bt periph;
   byte_bt spatz;
   byte_bt pulp;
+  byte_bt dram;
   byte_bt mbox;
 } carfield_slave_idx_t;
 
@@ -87,6 +90,7 @@ function automatic int unsigned gen_num_axi_slave(islands_cfg_t island_cfg);
   if (island_cfg.periph.enable  ) begin ret++; end
   if (island_cfg.spatz.enable   ) begin ret++; end
   if (island_cfg.pulp.enable    ) begin ret++; end
+  if (island_cfg.dram.enable    ) begin ret++; end
   if (island_cfg.mbox.enable    ) begin ret++; end
   return ret;
 endfunction
@@ -110,6 +114,8 @@ function automatic carfield_slave_idx_t carfield_gen_axi_slave_idx(islands_cfg_t
   end else begin ret.spatz = MaxExtAxiSlv + j; j++; end
   if (island_cfg.pulp.enable) begin ret.pulp = i; i++;
   end else begin ret.pulp = MaxExtAxiSlv + j; j++; end
+  if (island_cfg.dram.enable) begin ret.dram = i; i++;
+  end else begin ret.dram = MaxExtAxiSlv + j; j++; end
   if (island_cfg.mbox.enable) begin ret.mbox = i; i++;
   end else begin ret.mbox = MaxExtAxiSlv + j; j++; end
   return ret;
@@ -188,6 +194,12 @@ function automatic axi_struct_t carfield_gen_axi_map(int unsigned NumSlave  ,
     ret.AxiEnd[i] = island_cfg.pulp.base + island_cfg.pulp.size;
     if (i < NumSlave - 1) i++;
   end
+  if (island_cfg.dram.enable) begin
+    ret.AxiIdx[i] = idx.dram;
+    ret.AxiStart[i] = island_cfg.dram.base;
+    ret.AxiEnd[i] = island_cfg.dram.base + island_cfg.dram.size;
+    if (i < NumSlave - 1) i++;
+  end
   if (island_cfg.mbox.enable) begin
     ret.AxiIdx[i] = idx.mbox;
     ret.AxiStart[i] = island_cfg.mbox.base;
@@ -323,6 +335,7 @@ function automatic int unsigned gen_carfield_domains(islands_cfg_t island_cfg);
 endfunction
 
 localparam islands_cfg_t CarfieldIslandsCfg = '{
+  cheshire:      '{1, CheshireBase, CheshireSize},
   l2_port0:      '{L2Port0Enable, L2Port0Base, L2Port0Size},
   l2_port1:      '{L2Port1Enable, L2Port1Base, L2Port1Size},
   safed:         '{SafetyIslandEnable, SafetyIslandBase, SafetyIslandSize},
@@ -331,6 +344,7 @@ localparam islands_cfg_t CarfieldIslandsCfg = '{
   spatz:         '{SpatzClusterEnable, SpatzClusterBase, SpatzClusterSize},
   pulp:          '{PulpClusterEnable, PulpClusterBase, PulpClusterSize},
   secured:       '{SecurityIslandEnable, SecurityIslandBase, SecurityIslandSize},
+  dram:          '{DramEnable, DramBase, DramSize},
   mbox:          '{MailboxEnable, MailboxBase, MailboxSize}
 };
 
@@ -419,6 +433,7 @@ typedef enum byte_bt {
   PeriphsSlvIdx      = CarfieldAxiSlvIdx.periph,
   FPClusterSlvIdx    = CarfieldAxiSlvIdx.spatz,
   IntClusterSlvIdx   = CarfieldAxiSlvIdx.pulp,
+  DramSlvIdx         = CarfieldAxiSlvIdx.dram,
   MailboxSlvIdx      = CarfieldAxiSlvIdx.mbox
 } axi_slv_idx_t;
 
@@ -578,7 +593,7 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{
   AddrWidth         : 48,
   AxiDataWidth      : 64,
   AxiUserWidth      : 10,  // {CACHE_PARTITIONING(5[9:5]), ECC_ERROR(1[4:4]), ATOPS(4[3:0])}
-  AxiMstIdWidth     : 2,
+  AxiMstIdWidth     : 3,
   TFLenWidth        : 32,
   AxiMaxMstTrans    : 64,
   AxiMaxSlvTrans    : 64,
@@ -593,13 +608,13 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{
   RegAmoPostCut     : 1,
   RegAdaptMemCut    : 1,
   // External AXI ports (at most 8 ports and rules)
-  AxiExtNumMst      : CarfieldAxiNumMasters,
-  AxiExtNumSlv      : CarfieldAxiNumSlaves,
-  AxiExtNumRules    : CarfieldAxiNumSlaves,
+  AxiExtNumMst      : 1,
+  AxiExtNumSlv      : 1,
+  AxiExtNumRules    : 1,
   // External AXI region map
-  AxiExtRegionIdx   : CarfieldAxiMap.AxiIdx,
-  AxiExtRegionStart : CarfieldAxiMap.AxiStart,
-  AxiExtRegionEnd   : CarfieldAxiMap.AxiEnd,
+  AxiExtRegionIdx   : 'h0,
+  AxiExtRegionStart : CarfieldIslandsCfg.cheshire.base + CarfieldIslandsCfg.cheshire.size,
+  AxiExtRegionEnd   : CarfieldIslandsCfg.dram.base,
   // External reg slaves (at most 8 ports and rules)
   RegExtNumSlv      : NumTotalRegSlv,
   RegExtNumRules    : NumTotalRegSlv,
@@ -649,9 +664,9 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{
   LlcMaxWriteTxns   : 32,
   LlcAmoNumCuts     : 1,
   LlcAmoPostCut     : 1,
-  LlcOutConnect     : 1,
-  LlcOutRegionStart : 'h8000_0000,
-  LlcOutRegionEnd   : 'h1_0000_0000,
+  LlcOutConnect     : CarfieldIslandsCfg.dram.enable,
+  LlcOutRegionStart : CarfieldIslandsCfg.dram.base,
+  LlcOutRegionEnd   : CarfieldIslandsCfg.dram.base + CarfieldIslandsCfg.dram.size,
   LlcUserMsb        : 9,
   LlcUserLsb        : 5,
   LlcCachePartition : 1,
@@ -709,6 +724,8 @@ localparam int unsigned LogDepth   = 3;
 /* L2 Parameters */
 /*****************/
 localparam int unsigned NumL2Ports = (CarfieldIslandsCfg.l2_port1.enable) ? 2 : 1;
+localparam int unsigned L2PortId = (CarfieldIslandsCfg.l2_port1.enable) ? L2Port1SlvIdx
+                                                                        : L2Port0SlvIdx;
 localparam int unsigned L2MemSize = CarfieldIslandsCfg.l2_port0.size/2;
 localparam int unsigned L2NumRules = 4; // 2 rules per each access mode
                                         // (interleaved, non-interleaved)