Skip to content

Commit

Permalink
Merge remote-tracking branch 'origin/yt/thales-tapeout' into rt/align
Browse files Browse the repository at this point in the history
  • Loading branch information
ricted98 committed Sep 4, 2024
2 parents 39f280e + ea020c3 commit 3858860
Show file tree
Hide file tree
Showing 71 changed files with 21,172 additions and 636 deletions.
5 changes: 4 additions & 1 deletion .github/workflows/lint.yml
Original file line number Diff line number Diff line change
Expand Up @@ -27,9 +27,12 @@ jobs:
# Exclude generated headers (no license checker support for optional lines)
exclude_paths: |
sw/include/regs/*.h
sw/include/tasi.h
sw/tests/bare-metal/hostd/tasi_*
.dir-locals.el
utils/*
scripts/*
hw/padframe/*
lint-sv:
runs-on: ubuntu-latest
Expand All @@ -42,7 +45,7 @@ jobs:
uses: chipsalliance/verible-linter-action@main
with:
paths: hw
exclude_paths: hw/configs
exclude_paths: hw/configs hw/padframe
extra_args: "--waiver_files .github/verible.waiver"
github_token: ${{ secrets.GITHUB_TOKEN }}
fail_on_error: true
Expand Down
2 changes: 1 addition & 1 deletion Bender.local
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ overrides:
axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics.git , rev: 46d567cad5a614a82778702d48b3a789aed7711b } # branch: astral
apb: { git: "https://github.com/pulp-platform/apb.git" , version: 0.2.3 }
redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git" , rev: "9e31f7c6c24877eaf58279903e7a162b16c9a721" } # branch: astral-v0
hci: { git: "https://github.com/pulp-platform/hci.git" , version: 2.1.1 }
hci: { git: "https://github.com/pulp-platform/hci.git" , rev: "38fc2a7eea7978df52434e66ee04a40788fd86b7" } # branch: lg/ecc_rebase_v2.1.1
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git" , version: =0.2.13 }
riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git" , version: =0.8.0 }
idma: { git: "https://github.com/pulp-platform/idma.git" , version: 0.6.2 }
Expand Down
31 changes: 24 additions & 7 deletions Bender.lock
Original file line number Diff line number Diff line change
Expand Up @@ -260,14 +260,17 @@ packages:
dependencies:
- common_cells
hci:
revision: afe0220f9a2f132dc8655c48da05aae5121a570b
version: 2.1.1
revision: 38fc2a7eea7978df52434e66ee04a40788fd86b7
version: null
source:
Git: https://github.com/pulp-platform/hci.git
dependencies:
- cluster_interconnect
- common_cells
- hwpe-stream
- l2_tcdm_hybrid_interco
- redundancy_cells
- register_interface
hier-icache:
revision: 2886cb2a46cea3e2bd2d979b505d88fadfbe150c
version: null
Expand Down Expand Up @@ -361,14 +364,15 @@ packages:
dependencies:
- common_cells
neureka:
revision: b6141132d915b3fa5c1db712b730ac463a949a34
version: 1.0.0
revision: f23d22a2d630cf8e4d524c919bfd943ab9e4998d
version: null
source:
Git: https://github.com/pulp-platform/neureka.git
dependencies:
- hci
- hwpe-ctrl
- hwpe-stream
- register_interface
- zeroriscy
obi:
revision: 5321106817e177d6c16ecc4daa922b96b1bc946b
Expand All @@ -379,7 +383,7 @@ packages:
- common_cells
- common_verification
opentitan:
revision: 1466a339775f62ebec9fababe2859462bf9198b3
revision: cb163f0d8eefd896ceed8b83d2987e7feccf830e
version: null
source:
Git: https://github.com/pulp-platform/opentitan.git
Expand Down Expand Up @@ -417,7 +421,7 @@ packages:
- idma
- register_interface
pulp_cluster:
revision: 2cd26c4923570ae81297c06078a0cfcded1e761c
revision: 069d77e162a4b2be4132d429135656b54d5150ba
version: null
source:
Git: https://github.com/pulp-platform/pulp_cluster.git
Expand Down Expand Up @@ -447,7 +451,7 @@ packages:
- tech_cells_generic
- timer_unit
redmule:
revision: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99
revision: 9223ccc932e21d0667e9c2d30831db41eec9299e
version: null
source:
Git: https://github.com/pulp-platform/redmule.git
Expand All @@ -458,6 +462,7 @@ packages:
- hci
- hwpe-ctrl
- hwpe-stream
- register_interface
- tech_cells_generic
redundancy_cells:
revision: 9e31f7c6c24877eaf58279903e7a162b16c9a721
Expand Down Expand Up @@ -553,6 +558,12 @@ packages:
- hwpe-ctrl
- hwpe-stream
- ibex
spacewire:
revision: null
version: null
source:
Path: /usr/scratch2/lagrev5/mciani/astral-project/spacewire
dependencies: []
spatz:
revision: 98de97f24fe42675c9b4a8cc08354a03af57400a
version: null
Expand All @@ -567,6 +578,12 @@ packages:
- register_interface
- riscv-dbg
- tech_cells_generic
streamer:
revision: null
version: null
source:
Path: /usr/scratch2/lagrev5/mciani/astral-project/streamer
dependencies: []
tagger:
revision: b288376b65b6bbd5feea196bb3c220f783d96e29
version: null
Expand Down
57 changes: 51 additions & 6 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,8 @@ dependencies:
hyperbus: { git: https://github.com/pulp-platform/hyperbus.git, rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh
dyn_mem: { git: https://github.com/pulp-platform/dyn_spm.git, rev: 480590062742230dc9bd4050358a15b4747bdf34 } # branch: main
safety_island: { git: https://github.com/pulp-platform/safety_island.git, rev: aaef55c798ab53560faaf451a86668fa1e6d0f3b } # branch: carfield
pulp_cluster: { git: https://github.com/pulp-platform/pulp_cluster.git, rev: 2cd26c4923570ae81297c06078a0cfcded1e761c } # branch: astral
opentitan: { git: https://github.com/pulp-platform/opentitan.git, rev: 1466a339775f62ebec9fababe2859462bf9198b3 } # branch: mc/astral
pulp_cluster: { git: https://github.com/pulp-platform/pulp_cluster.git, rev: 069d77e162a4b2be4132d429135656b54d5150ba } # branch: astral
opentitan: { git: https://github.com/pulp-platform/opentitan.git, rev: cb163f0d8eefd896ceed8b83d2987e7feccf830e } # branch: mc/astral
mailbox_unit: { git: https://github.com/pulp-platform/mailbox_unit.git, version: 1.1.0 }
apb: { git: https://github.com/pulp-platform/apb.git, version: 0.2.3 }
timer_unit: { git: https://github.com/pulp-platform/timer_unit.git, version: 1.0.2 }
Expand All @@ -28,6 +28,8 @@ dependencies:
common_cells: { git: https://github.com/pulp-platform/common_cells.git, version: 1.37.0 } # branch: master
pulp-ethernet: { git: https://github.com/pulp-platform/pulp-ethernet.git, rev: 1f8f1776ec494773f8e6c48e16685eb35d5f445e } # branch: handshake
riscv-dbg: { git: https://github.com/pulp-platform/riscv-dbg.git, version: =0.8.0 }
streamer: { path: /usr/scratch2/lagrev5/mciani/astral-project/streamer }
spacewire: { path: /usr/scratch2/lagrev5/mciani/astral-project/spacewire }

workspace:
package_links:
Expand All @@ -44,6 +46,10 @@ sources:
files:
- hw/configs/carfield_l2dual_secure_pulp_periph_can.sv

- target: carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw
files:
- hw/configs/carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw.sv

- target: carfield_l2dual_safe_secure_pulp_spatz_periph_can
files:
- hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv
Expand Down Expand Up @@ -85,8 +91,18 @@ sources:
# levels 1 and 0, etc. Files within a level are ordered alphabetically.
# Level 0
- hw/carfield_pkg.sv
- hw/carfield_chip_pkg.sv
- hw/regs/carfield_reg_pkg.sv
- hw/regs/carfield_reg_top.sv
- hw/padframe/astral_padframe/src/pkg_astral_padframe.sv
- hw/padframe/astral_padframe/src/pkg_internal_astral_padframe_periph.sv
- hw/padframe/astral_padframe/src/astral_padframe_periph_config_reg_pkg.sv
- hw/padframe/astral_padframe/src/astral_padframe_periph_config_reg_top.sv
- hw/padframe/astral_padframe/src/astral_padframe_periph_pads.sv
- hw/padframe/astral_padframe/src/astral_padframe_periph_muxer.sv
- hw/padframe/astral_padframe/src/astral_padframe_periph.sv
- hw/padframe/astral_padframe/src/astral_padframe.sv
- hw/padframe/pad_behav.sv
# Level 1
- hw/cheshire_wrap.sv
- hw/hyperbus_wrap.sv
Expand All @@ -95,6 +111,7 @@ sources:
- hw/carfield_rstgen.sv
# Level 2
- hw/carfield.sv
- hw/astral_wrap.sv

- target: spatz
files:
Expand All @@ -104,8 +121,8 @@ sources:
files:
- target/sim/src/hyp_vip/s27ks0641.v
- target/sim/src/vip_carfield_soc.sv
- target/sim/src/carfield_fix.sv
- target/sim/src/carfield_tb.sv
- target/sim/src/astral_fix.sv
- target/sim/src/astral_tb.sv

- target: spyglass
files:
Expand All @@ -115,27 +132,55 @@ sources:
files:
- tech/sourcecode/tc_clk.sv
- tech/sourcecode/tc_sram.sv
- tech/sourcecode/ptme_ram.sv
- tech/sourcecode/configurable_delay.sv
- target/synth/src/carfield_synth_wrap.sv
- tech/sourcecode/gf12_fll_wrap.sv

- target: tech_sim
files:
# TODO: add technology dependent memory cells
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_128x40m2b1w0.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x32m2b1w1.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x39m4b1w0.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x44m2b1w1.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x46m2b1w1.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x64m2b1w1.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x128m2b1w1.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x144m1b1w0.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_1024x39m4b1w0.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_512x39m4b1w0.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_1024x64m4b1w1.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_128x264m1b1w0.v
- tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_1024x39m4b1w0.v
- tech/sourcecode/macros/sram_dp_hse_rvt_mvt_16384x8m16b8w1.v
- tech/sourcecode/macros/sram_sp_hse_rvt_mvt_2560x76m4b4w0.v
- tech/sourcecode/macros/sram_sp_hse_rvt_mvt_4096x76m4b4w0.v
- tech/sourcecode/macros/sram_sp_hse_rvt_mvt_16384x39m8b8w0.v
- tech/sourcecode/tc_sram.sv
# FLL Model
- tech/sourcecode/fll/rtl/FLL_digital/FLLPkg.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_clk_divider.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_clk_period_quantizer.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_clock_gated.gf12.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_clock_gated.rtl.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_dither_pattern_gen.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_glitchfree_clkdiv.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_glitchfree_clkmux.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_loop_filter.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_mux.gf12.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_mux.rtl.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_reg.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_settling_monitor.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_synchroedge.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_zerodelta.vhd
- tech/sourcecode/fll/rtl/FLL_digital/FLL_digital.vhd
- tech/sourcecode/fll/rtl/behavioral/gf12_FLL_DCO_model.tc.vhd
#- tech/sourcecode/fll/rtl/behavioral/gf12_FLL_DCO_model.vhd
- tech/sourcecode/fll/rtl/behavioral/gf12_FLL_model.vhd
- tech/sourcecode/fll/rtl/behavioral/gf12_FLL.v
- tech/sourcecode/gf12_fll_wrap.sv
# PAD Model
- tech/sourcecode/pad/io_gppr_12lpplus_t18_mv08_mv18_fs18_rvt_dr.v
- tech/sourcecode/ptme_ram.sv

- target: all(xilinx, fpga, xilinx_vanilla)
files:
Expand Down
10 changes: 7 additions & 3 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -32,20 +32,24 @@ floating-point and integer workloads.
[Targets](https://pulp-platform.github.io/carfield/tg).
* For detailed information on Carfield's inner workings, consult the [User
Manual](https://pulp-platform.github.io/carfield/um/).


If you are impatient and have all needed
[dependencies](https://pulp-platform.github.io/carfield/gs/#dependencies), type:

```
make car-all
source env/env-iis.sh
bender update
make car-all PYTHON=python3
make tech-init
```

and then run a [simulation](https://pulp-platform.github.io/carfield/tg/sim) with Questasim by
typing:

```tcl
make car-vsim-sim-build
make car-vsim-sim-run CHS_BINARY=./sw/tests/bare-metal/hostd/helloworld.car.l2.elf
make car-vsim-sim-build DEBUG=1 TECH_SIM=1
make car-vsim-sim-run CHS_BINARY=./sw/tests/bare-metal/hostd/helloworld.car.l2.elf DEBUG=1 TECH_SIM=1
```

---
Expand Down
2 changes: 1 addition & 1 deletion bender-common.mk
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
# Author: Matteo Perotti <[email protected]>

# Runtime-selectable Carfield configuration
CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can
CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw

# bender targets
common_targs += -t cva6
Expand Down
1 change: 1 addition & 0 deletions bender-sim.mk
Original file line number Diff line number Diff line change
Expand Up @@ -13,4 +13,5 @@ ifeq ($(TECH_SIM), 1)
sim_targs += -t tech_sim
sim_defs += -D INITIALIZE_MEMORY
sim_defs += -D INITIALIZE_OUTPUT
sim_defs += -D GF12_FLL
endif
1 change: 1 addition & 0 deletions bender-synth.mk
Original file line number Diff line number Diff line change
Expand Up @@ -17,3 +17,4 @@ synth_defs += -D SYNTHESIS
synth_defs += -D EXCLUDE_PADFRAME
synth_defs += -D TARGET_INTEL16_SIMPLE_DPM_RF
synth_defs += -D NO_SYNOPSYS_FF
synth_defs += -D GF12_FLL
41 changes: 38 additions & 3 deletions carfield.mk
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@
CAR_ROOT ?= $(shell $(BENDER) path carfield)
CAR_HW_DIR := $(CAR_ROOT)/hw
CAR_SW_DIR := $(CAR_ROOT)/sw
CAR_TGT_DIR := $(CAR_ROOT)/target/
CAR_TGT_DIR := $(CAR_ROOT)/target
CAR_XIL_DIR := $(CAR_TGT_DIR)/xilinx
CAR_SIM_DIR := $(CAR_TGT_DIR)/sim
SECD_ROOT ?= $(shell $(BENDER) path opentitan)
Expand All @@ -36,6 +36,8 @@ BENDER_PATH ?= $(shell which $(BENDER))

PYTHON ?= python3

PADRICK ?= $(CAR_HW_DIR)/padframe/padrick

# Include mandatory bender targets and defines for multiple targets (sim, fpga, synth)
include $(CAR_ROOT)/bender-common.mk
include $(CAR_ROOT)/bender-sim.mk
Expand Down Expand Up @@ -100,6 +102,15 @@ SPATZD_MAKEDIR := $(SPATZD_ROOT)/hw/system/spatz_cluster
SPATZD_BINARY ?=
SPATZD_BOOTMODE ?= 0 # default jtag bootmode

# Streamer, implementing telecommand and telemetry protocols
STREAMER_ROOT ?= $(shell $(BENDER) path streamer)

# SpaceWire IP
SPACEWIRE_ROOT ?= $(shell $(BENDER) path spacewire)

# PLL/FLL bypass
BYPASS_PLL ?= 0

###########################
# System HW configuration #
###########################
Expand Down Expand Up @@ -167,7 +178,7 @@ SAFED_SW_BUILD := safed-sw-build
SAFED_SW_INIT := safed-sw-init
endif

ifeq ($(shell echo $(SAFED_PRESENT)), 1)
ifeq ($(shell echo $(SPATZD_PRESENT)), 1)
SPATZD_HW_INIT := spatzd-hw-init
endif

Expand Down Expand Up @@ -246,6 +257,30 @@ secd-hw-init:
## not forget to check in the generated RTL. In addition, dedicated documentation is autogenerated.
regenerate_soc_regs: $(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv $(CAR_ROOT)/hw/regs/carfield_reg_top.sv $(CAR_SW_DIR)/include/regs/soc_ctrl.h $(CAR_HW_DIR)/regs/pcr.md

.PHONY: $(CAR_ROOT)/hw/regs/carfield_regs.hjson
$(CAR_ROOT)/hw/regs/carfield_regs.hjson: hw/regs/carfield_regs.csv | venv
$(VENV)/$(PYTHON) ./scripts/csv_to_json.py --input $< --output $@

.PHONY: $(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv hw/regs/carfield_reg_top.sv
$(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv $(CAR_ROOT)/hw/regs/carfield_reg_top.sv: $(CAR_ROOT)/hw/regs/carfield_regs.hjson | venv
$(VENV)/$(PYTHON) utils/reggen/regtool.py -r $< --outdir $(dir $@)

.PHONY: $(CAR_SW_DIR)/include/regs/soc_ctrl.h
$(CAR_SW_DIR)/include/regs/soc_ctrl.h: $(CAR_ROOT)/hw/regs/carfield_regs.hjson | venv
$(VENV)/$(PYTHON) utils/reggen/regtool.py -D $< > $@

.PHONY: $(CAR_SW_DIR)/hw/regs/pcr.md
$(CAR_HW_DIR)/regs/pcr.md: $(CAR_ROOT)/hw/regs/carfield_regs.hjson | venv
$(VENV)/$(PYTHON) utils/reggen/regtool.py -d $< > $@

## @section Carfield padframe generation
.PHONY: regenerate_padframe
regenerate_padframe: $(CAR_HW_DIR)/padframe/astral_padframe

$(CAR_HW_DIR)/padframe/astral_padframe: $(CAR_HW_DIR)/padframe/astral_padframe.yml
$(PADRICK) generate rtl $< -o $@
sed -i.original '/i_pad_vss_core_v_2/d' $@/src/astral_padframe_periph_pads.sv

.PHONY: $(CAR_ROOT)/hw/regs/carfield_regs.hjson
$(CAR_ROOT)/hw/regs/carfield_regs.hjson: hw/regs/carfield_regs.csv | venv
$(VENV)/$(PYTHON) ./scripts/csv_to_json.py --input $< --output $@
Expand Down Expand Up @@ -387,7 +422,7 @@ car-check-litmus-tests: $(LITMUS_WORK_DIR)/litmus.log
##############
tech-repo := [email protected]:Astral/gf12.git
# no commit by default, change during development
tech-commit := 0939b49dc4517fdbba792ab046b8700aa8ae9026
tech-commit := 9fe2a2bcb7a636c93bceada37e23bfc08902b6b3 # branch: yt/thales

tech-clone:
git clone $(tech-repo) tech
Expand Down
Loading

0 comments on commit 3858860

Please sign in to comment.