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Implemented pad muxing and FLL configuration in ethernet test; Improv…
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…ed readability of memory map (#48)

Co-authored-by: Victor Isachi <[email protected]>
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@VictorIsachi
VictorIsachi and Victor Isachi authored Sep 2, 2024
1 parent 7f1b9cc commit e359c13
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132 changes: 67 additions & 65 deletions sw/include/car_memory_map.h
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Original file line number Diff line number Diff line change
Expand Up @@ -205,72 +205,54 @@ extern void *__base_l2;
// Padframe
#define PADFRAME_BASE_ADDRESS padframe

#define PADFRAME_CONFIG_INFO 0x0
#define PADFRAME_CONFIG_MUXED_V_00_CFG 0x4
#define PADFRAME_CONFIG_MUXED_V_00_MUX_SEL 0x8
#define PADFRAME_CONFIG_MUXED_V_01_CFG 0xc
#define PADFRAME_CONFIG_MUXED_V_01_MUX_SEL 0x10
#define PADFRAME_CONFIG_MUXED_V_02_CFG 0x14
#define PADFRAME_CONFIG_MUXED_V_02_MUX_SEL 0x18
#define PADFRAME_CONFIG_MUXED_V_03_CFG 0x1c
#define PADFRAME_CONFIG_MUXED_V_03_MUX_SEL 0x20
#define PADFRAME_CONFIG_MUXED_V_04_CFG 0x24
#define PADFRAME_CONFIG_MUXED_V_04_MUX_SEL 0x28
#define PADFRAME_CONFIG_MUXED_V_05_CFG 0x2c
#define PADFRAME_CONFIG_MUXED_V_05_MUX_SEL 0x30
#define PADFRAME_CONFIG_MUXED_V_06_CFG 0x34
#define PADFRAME_CONFIG_MUXED_V_06_MUX_SEL 0x38
#define PADFRAME_CONFIG_MUXED_V_07_CFG 0x3c
#define PADFRAME_CONFIG_MUXED_V_07_MUX_SEL 0x40
#define PADFRAME_CONFIG_MUXED_V_08_CFG 0x44
#define PADFRAME_CONFIG_MUXED_V_08_MUX_SEL 0x48
#define PADFRAME_CONFIG_MUXED_V_09_CFG 0x4c
#define PADFRAME_CONFIG_MUXED_V_09_MUX_SEL 0x50
#define PADFRAME_CONFIG_MUXED_V_10_CFG 0x54
#define PADFRAME_CONFIG_MUXED_V_10_MUX_SEL 0x58
#define PADFRAME_CONFIG_MUXED_V_11_CFG 0x5c
#define PADFRAME_CONFIG_MUXED_V_11_MUX_SEL 0x60
#define PADFRAME_CONFIG_MUXED_V_12_CFG 0x64
#define PADFRAME_CONFIG_MUXED_V_12_MUX_SEL 0x68
#define PADFRAME_CONFIG_MUXED_V_13_CFG 0x6c
#define PADFRAME_CONFIG_MUXED_V_13_MUX_SEL 0x70
#define PADFRAME_CONFIG_MUXED_V_14_CFG 0x74
#define PADFRAME_CONFIG_MUXED_V_14_MUX_SEL 0x78
#define PADFRAME_CONFIG_MUXED_V_15_CFG 0x7c
#define PADFRAME_CONFIG_MUXED_V_15_MUX_SEL 0x80
#define PADFRAME_CONFIG_MUXED_V_16_CFG 0x84
#define PADFRAME_CONFIG_MUXED_V_16_MUX_SEL 0x88
#define PADFRAME_CONFIG_MUXED_V_17_CFG 0x8c
#define PADFRAME_CONFIG_MUXED_V_17_MUX_SEL 0x90
#define PADFRAME_CONFIG_MUXED_H_00_CFG 0x94
#define PADFRAME_CONFIG_MUXED_H_00_MUX_SEL 0x98
#define PADFRAME_CONFIG_MUXED_H_01_CFG 0x9c
#define PADFRAME_CONFIG_MUXED_H_01_MUX_SEL 0xa0
#define PADFRAME_CONFIG_MUXED_H_02_CFG 0xa4
#define PADFRAME_CONFIG_MUXED_H_02_MUX_SEL 0xa8
#define PADFRAME_CONFIG_MUXED_H_03_CFG 0xac
#define PADFRAME_CONFIG_MUXED_H_03_MUX_SEL 0xb0
#define PADFRAME_CONFIG_INFO 0x0

#define PADFRAME_CONFIG_MUXED_V_00_CFG 0x4
#define PADFRAME_CONFIG_MUXED_V_01_CFG 0xc
#define PADFRAME_CONFIG_MUXED_V_02_CFG 0x14
#define PADFRAME_CONFIG_MUXED_V_03_CFG 0x1c
#define PADFRAME_CONFIG_MUXED_V_04_CFG 0x24
#define PADFRAME_CONFIG_MUXED_V_05_CFG 0x2c
#define PADFRAME_CONFIG_MUXED_V_06_CFG 0x34
#define PADFRAME_CONFIG_MUXED_V_07_CFG 0x3c
#define PADFRAME_CONFIG_MUXED_V_08_CFG 0x44
#define PADFRAME_CONFIG_MUXED_V_09_CFG 0x4c
#define PADFRAME_CONFIG_MUXED_V_10_CFG 0x54
#define PADFRAME_CONFIG_MUXED_V_11_CFG 0x5c
#define PADFRAME_CONFIG_MUXED_V_12_CFG 0x64
#define PADFRAME_CONFIG_MUXED_V_13_CFG 0x6c
#define PADFRAME_CONFIG_MUXED_V_14_CFG 0x74
#define PADFRAME_CONFIG_MUXED_V_15_CFG 0x7c
#define PADFRAME_CONFIG_MUXED_V_16_CFG 0x84
#define PADFRAME_CONFIG_MUXED_V_17_CFG 0x8c
#define PADFRAME_CONFIG_MUXED_H_00_CFG 0x94
#define PADFRAME_CONFIG_MUXED_H_01_CFG 0x9c
#define PADFRAME_CONFIG_MUXED_H_02_CFG 0xa4
#define PADFRAME_CONFIG_MUXED_H_03_CFG 0xac

#define PADFRAME_CONFIG_MUXED_V_00_MUX_SEL 0x8
#define PADFRAME_CONFIG_MUXED_V_01_MUX_SEL 0x10
#define PADFRAME_CONFIG_MUXED_V_02_MUX_SEL 0x18
#define PADFRAME_CONFIG_MUXED_V_03_MUX_SEL 0x20
#define PADFRAME_CONFIG_MUXED_V_04_MUX_SEL 0x28
#define PADFRAME_CONFIG_MUXED_V_05_MUX_SEL 0x30
#define PADFRAME_CONFIG_MUXED_V_06_MUX_SEL 0x38
#define PADFRAME_CONFIG_MUXED_V_07_MUX_SEL 0x40
#define PADFRAME_CONFIG_MUXED_V_08_MUX_SEL 0x48
#define PADFRAME_CONFIG_MUXED_V_09_MUX_SEL 0x50
#define PADFRAME_CONFIG_MUXED_V_10_MUX_SEL 0x58
#define PADFRAME_CONFIG_MUXED_V_11_MUX_SEL 0x60
#define PADFRAME_CONFIG_MUXED_V_12_MUX_SEL 0x68
#define PADFRAME_CONFIG_MUXED_V_13_MUX_SEL 0x70
#define PADFRAME_CONFIG_MUXED_V_14_MUX_SEL 0x78
#define PADFRAME_CONFIG_MUXED_V_15_MUX_SEL 0x80
#define PADFRAME_CONFIG_MUXED_V_16_MUX_SEL 0x88
#define PADFRAME_CONFIG_MUXED_V_17_MUX_SEL 0x90
#define PADFRAME_CONFIG_MUXED_H_00_MUX_SEL 0x98
#define PADFRAME_CONFIG_MUXED_H_01_MUX_SEL 0xa0
#define PADFRAME_CONFIG_MUXED_H_02_MUX_SEL 0xa8
#define PADFRAME_CONFIG_MUXED_H_03_MUX_SEL 0xb0

#define PADFRAME_MUXED_H_00_SEL_DEFAULT 0x0
#define PADFRAME_MUXED_H_00_SEL_ETHERNET_TXD_3 0x1
#define PADFRAME_MUXED_H_00_SEL_GPIO_IO_H_0 0x2
#define PADFRAME_MUXED_H_00_SEL_HPC_SAMPLE 0x3
#define PADFRAME_MUXED_H_00_SEL_SERIAL_LINK_O_H_0 0x4
#define PADFRAME_MUXED_H_01_SEL_DEFAULT 0x0
#define PADFRAME_MUXED_H_01_SEL_ETHERNET_MD 0x1
#define PADFRAME_MUXED_H_01_SEL_GPIO_IO_H_1 0x2
#define PADFRAME_MUXED_H_01_SEL_LLC_LINE_0 0x3
#define PADFRAME_MUXED_H_01_SEL_SERIAL_LINK_O_H_1 0x4
#define PADFRAME_MUXED_H_02_SEL_DEFAULT 0x0
#define PADFRAME_MUXED_H_02_SEL_ETHERNET_MDC 0x1
#define PADFRAME_MUXED_H_02_SEL_GPIO_IO_H_2 0x2
#define PADFRAME_MUXED_H_02_SEL_LLC_LINE_1 0x3
#define PADFRAME_MUXED_H_02_SEL_SERIAL_LINK_O_H_2 0x4
#define PADFRAME_MUXED_H_03_SEL_DEFAULT 0x0
#define PADFRAME_MUXED_H_03_SEL_ETHERNET_RST_N 0x1
#define PADFRAME_MUXED_H_03_SEL_GPIO_IO_H_3 0x2
#define PADFRAME_MUXED_H_03_SEL_OBT_EXT_CLK 0x3
#define PADFRAME_MUXED_H_03_SEL_SERIAL_LINK_O_H_3 0x4
#define PADFRAME_MUXED_V_00_SEL_DEFAULT 0x0
#define PADFRAME_MUXED_V_00_SEL_CAN_RX 0x1
#define PADFRAME_MUXED_V_00_SEL_GPIO_IO_V_0 0x2
Expand Down Expand Up @@ -367,6 +349,26 @@ extern void *__base_l2;
#define PADFRAME_MUXED_V_17_SEL_GPIO_IO_V_17 0x2
#define PADFRAME_MUXED_V_17_SEL_HPC_CMD_EN 0x3
#define PADFRAME_MUXED_V_17_SEL_SERIAL_LINK_O_V_3 0x4
#define PADFRAME_MUXED_H_00_SEL_DEFAULT 0x0
#define PADFRAME_MUXED_H_00_SEL_ETHERNET_TXD_3 0x1
#define PADFRAME_MUXED_H_00_SEL_GPIO_IO_H_0 0x2
#define PADFRAME_MUXED_H_00_SEL_HPC_SAMPLE 0x3
#define PADFRAME_MUXED_H_00_SEL_SERIAL_LINK_O_H_0 0x4
#define PADFRAME_MUXED_H_01_SEL_DEFAULT 0x0
#define PADFRAME_MUXED_H_01_SEL_ETHERNET_MD 0x1
#define PADFRAME_MUXED_H_01_SEL_GPIO_IO_H_1 0x2
#define PADFRAME_MUXED_H_01_SEL_LLC_LINE_0 0x3
#define PADFRAME_MUXED_H_01_SEL_SERIAL_LINK_O_H_1 0x4
#define PADFRAME_MUXED_H_02_SEL_DEFAULT 0x0
#define PADFRAME_MUXED_H_02_SEL_ETHERNET_MDC 0x1
#define PADFRAME_MUXED_H_02_SEL_GPIO_IO_H_2 0x2
#define PADFRAME_MUXED_H_02_SEL_LLC_LINE_1 0x3
#define PADFRAME_MUXED_H_02_SEL_SERIAL_LINK_O_H_2 0x4
#define PADFRAME_MUXED_H_03_SEL_DEFAULT 0x0
#define PADFRAME_MUXED_H_03_SEL_ETHERNET_RST_N 0x1
#define PADFRAME_MUXED_H_03_SEL_GPIO_IO_H_3 0x2
#define PADFRAME_MUXED_H_03_SEL_OBT_EXT_CLK 0x3
#define PADFRAME_MUXED_H_03_SEL_SERIAL_LINK_O_H_3 0x4

// Error codes
#define EHOSTDEXEC 1 // Execution error host domain
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46 changes: 46 additions & 0 deletions sw/tests/bare-metal/hostd/ethernet.c
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,8 @@
#include "params.h"
#include "printf.h"
#include "util.h"
#include "padframe.h"
#include "fll.h"

static dif_rv_plic_t plic0;

Expand Down Expand Up @@ -47,11 +49,55 @@ static dif_rv_plic_t plic0;
#define L2_TX_BASE 0x78000000
#define L2_RX_BASE 0x78001000

#define FLL_WAIT_CYCLES 10000

int main(void) {

// Put SMP Hart to sleep
if (hart_id() != 0) wfi();

// Configuring padframe - mux
write_padframe_mux(PADFRAME_CONFIG_MUXED_V_07_MUX_SEL, PADFRAME_MUXED_V_07_SEL_ETHERNET_RXCK);
write_padframe_mux(PADFRAME_CONFIG_MUXED_V_08_MUX_SEL, PADFRAME_MUXED_V_08_SEL_ETHERNET_RXCTL);
write_padframe_mux(PADFRAME_CONFIG_MUXED_V_09_MUX_SEL, PADFRAME_MUXED_V_09_SEL_ETHERNET_RXD_0);
write_padframe_mux(PADFRAME_CONFIG_MUXED_V_10_MUX_SEL, PADFRAME_MUXED_V_10_SEL_ETHERNET_RXD_1);
write_padframe_mux(PADFRAME_CONFIG_MUXED_V_11_MUX_SEL, PADFRAME_MUXED_V_11_SEL_ETHERNET_RXD_2);
write_padframe_mux(PADFRAME_CONFIG_MUXED_V_12_MUX_SEL, PADFRAME_MUXED_V_12_SEL_ETHERNET_RXD_3);
write_padframe_mux(PADFRAME_CONFIG_MUXED_V_13_MUX_SEL, PADFRAME_MUXED_V_13_SEL_ETHERNET_TXCK);
write_padframe_mux(PADFRAME_CONFIG_MUXED_V_14_MUX_SEL, PADFRAME_MUXED_V_14_SEL_ETHERNET_TXCTL);
write_padframe_mux(PADFRAME_CONFIG_MUXED_V_15_MUX_SEL, PADFRAME_MUXED_V_15_SEL_ETHERNET_TXD_0);
write_padframe_mux(PADFRAME_CONFIG_MUXED_V_16_MUX_SEL, PADFRAME_MUXED_V_16_SEL_ETHERNET_TXD_1);
write_padframe_mux(PADFRAME_CONFIG_MUXED_V_17_MUX_SEL, PADFRAME_MUXED_V_17_SEL_ETHERNET_TXD_2);
write_padframe_mux(PADFRAME_CONFIG_MUXED_H_00_MUX_SEL, PADFRAME_MUXED_H_00_SEL_ETHERNET_TXD_3);
write_padframe_mux(PADFRAME_CONFIG_MUXED_H_01_MUX_SEL, PADFRAME_MUXED_H_01_SEL_ETHERNET_MD);
write_padframe_mux(PADFRAME_CONFIG_MUXED_H_02_MUX_SEL, PADFRAME_MUXED_H_02_SEL_ETHERNET_MDC);
write_padframe_mux(PADFRAME_CONFIG_MUXED_H_03_MUX_SEL, PADFRAME_MUXED_H_03_SEL_ETHERNET_RST_N);
// Configuring padframe - pullup
write_padframe_pen(PADFRAME_CONFIG_MUXED_V_07_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_07_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_V_08_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_08_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_V_09_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_09_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_V_10_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_10_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_V_11_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_11_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_V_12_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_12_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_V_13_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_13_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_V_14_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_14_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_V_15_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_15_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_V_16_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_16_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_V_17_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_17_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_H_00_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_00_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_H_01_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_01_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_H_02_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_02_CFG, 0x1);
write_padframe_pen(PADFRAME_CONFIG_MUXED_H_03_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_03_CFG, 0x1);

// Configuring FLL
fll_normal(FLL_PERIPH_ID);
set_fll_clk_mul(0x3E7, FLL_PERIPH_ID);
set_fll_clk_div(0x2, FLL_PERIPH_ID);

// Wait for FLL clk out to stabilize
for (int i = 0; i < FLL_WAIT_CYCLES; i++)
asm volatile("addi x0, x0, 0" ::);

int prio = 0x1;
bool t;
unsigned global_irq_en = 0x00001808;
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