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WIP: new_usb added (empty shell): various parameter changes
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@fhaus1
fhaus1 committed Oct 30, 2024
1 parent d85000d commit 034eb01
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24 changes: 15 additions & 9 deletions hw/cheshire_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@
// Paul Scheffler <[email protected]>
// Thomas Benz <[email protected]>
// Alessandro Ottaviano <[email protected]>
// Fabian Hauser <[email protected]>

package cheshire_pkg;

Expand All @@ -26,13 +27,16 @@ package cheshire_pkg;
localparam int unsigned MaxExtRegSlvWidth = 4;

// Parameters defined by generated hardware (regenerate to adapt)
localparam int unsigned SpihNumCs = spi_host_reg_pkg::NumCS - 1; // Last CS is dummy
localparam int unsigned SlinkNumChan = serial_link_single_channel_reg_pkg::NumChannels;
localparam int unsigned SlinkNumLanes = serial_link_single_channel_reg_pkg::NumBits/2;
localparam int unsigned SlinkMaxClkDiv = 1 << serial_link_single_channel_reg_pkg::Log2MaxClkDiv;
localparam int unsigned ClintNumCores = clint_reg_pkg::NumCores;
localparam int unsigned UsbNumPorts = spinal_usb_ohci_pkg::NumPhyPorts;
localparam int unsigned NewUsbNumPorts = new_usb_ohci_pkg::NumPhyPorts;
localparam int unsigned SpihNumCs = spi_host_reg_pkg::NumCS - 1; // Last CS is dummy
localparam int unsigned SlinkNumChan = serial_link_single_channel_reg_pkg::NumChannels;
localparam int unsigned SlinkNumLanes = serial_link_single_channel_reg_pkg::NumBits/2;
localparam int unsigned SlinkMaxClkDiv = 1 << serial_link_single_channel_reg_pkg::Log2MaxClkDiv;
localparam int unsigned ClintNumCores = clint_reg_pkg::NumCores;
localparam int unsigned NewUsbNumPorts = new_usb_ohci_pkg::NumPhyPorts;
localparam int unsigned SpinalUsbNumPorts_max = spinal_usb_ohci_pkg::NumPhyPorts; //The available port number is fixed because the SpinalUSB is already generated

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[verible-verilog-lint] hw/cheshire_pkg.sv#L36 

Localparam name does not match the naming convention defined by regex pattern: (([A-Z0-9]+[a-z0-9]*)+(_[0-9]+)?) [Style: constants] [parameter-name-style]
Raw output 
message:"Localparam name does not match the naming convention defined by regex pattern: (([A-Z0-9]+[a-z0-9]*)+(_[0-9]+)?) [Style: constants] [parameter-name-style]"  location:{path:"hw/cheshire_pkg.sv"  range:{start:{line:36  column:27}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
localparam int unsigned SpinalUsbNumPorts = 2; //Select how many of the SpinalUsbNumPorts_max ports you want to use. The rest is tied to zero.
localparam int unsigned UsbNumPorts = NewUsbNumPorts + SpinalUsbNumPorts;


// Default JTAG ID code type
typedef struct packed {
Expand Down Expand Up @@ -180,8 +184,8 @@ package cheshire_pkg;
dw_bt UsbDmaMaxReads;
doub_bt UsbAddrMask;
doub_bt UsbAddrDomain;
// TODO: parameter for NewUsb (FIFO depth...)
/// ...
// Parameter for NewUsb
dw_bt NewUsbDmaMaxReads;
// Parameters for DMA
dw_bt DmaConfMaxReadTxns;
dw_bt DmaConfMaxWriteTxns;
Expand Down Expand Up @@ -662,6 +666,8 @@ package cheshire_pkg;
UsbDmaMaxReads : 16,
UsbAddrMask : 'hFFFF_FFFF,
UsbAddrDomain : 'h0000_0000,
// NewUSB config
NewUsbDmaMaxReads : 16,
// DMA config
DmaConfMaxReadTxns : 4,
DmaConfMaxWriteTxns : 4,
Expand Down
84 changes: 29 additions & 55 deletions hw/cheshire_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@
// Paul Scheffler <[email protected]>
// Thomas Benz <[email protected]>
// Alessandro Ottaviano <[email protected]>
// Fabian Hauser <[email protected]>

module cheshire_soc import cheshire_pkg::*; #(
// Cheshire config
Expand Down Expand Up @@ -1694,22 +1695,22 @@ module cheshire_soc import cheshire_pkg::*; #(
.dma_req_o ( axi_in_req[AxiIn.usb] ),
.dma_rsp_i ( axi_in_rsp[AxiIn.usb] ),
.intr_o ( intr.intn.usb ),
.phy_clk_i ( usb_clk_i ),
.phy_rst_ni ( usb_rst_ni ),
.phy_dm_i ( usb_dm_i ),
.phy_dm_o ( usb_dm_o ),
.phy_dm_oe_o ( usb_dm_oe_o ),
.phy_dp_i ( usb_dp_i ),
.phy_dp_o ( usb_dp_o ),
.phy_dp_oe_o ( usb_dp_oe_o )
.phy_clk_i ( usb_clk_i ),
.phy_rst_ni ( usb_rst_ni ),
.phy_dm_i ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'b0, usb_dm_i [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),
.phy_dm_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'bX, usb_dm_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),
.phy_dm_oe_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'bX, usb_dm_oe_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),
.phy_dp_i ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'b0, usb_dp_i [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),
.phy_dp_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'bX, usb_dp_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),
.phy_dp_oe_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'bX, usb_dp_oe_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } )
);

end else begin : gen_no_usb

assign usb_dm_o = '0;
assign usb_dm_oe_o = '0;
assign usb_dp_o = '0;
assign usb_dp_oe_o = '0;
assign usb_dm_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] = '0;
assign usb_dm_oe_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] = '0;
assign usb_dp_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] = '0;
assign usb_dp_oe_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] = '0;

assign intr.intn.usb = 0;

Expand All @@ -1723,6 +1724,10 @@ module cheshire_soc import cheshire_pkg::*; #(

// TODO: USB has no internal error handling, so it should have a bus error unit.

// TODO: Test out different port numbers,
// currently 4 phyports, (2,3) are connected to spinal (0,1), spinal (2,3) tied to zero
// currently 4 phyports, (0,1) are connected to newusb (0,1)

new_usb_ohci #(
.AxiMaxReads ( Cfg.UsbDmaMaxReads ),
.AxiAddrWidth ( Cfg.AddrWidth ),
Expand All @@ -1731,8 +1736,6 @@ module cheshire_soc import cheshire_pkg::*; #(
.AxiUserWidth ( Cfg.AxiUserWidth ),
.AxiId ( '0 ),
.AxiUser ( Cfg.AxiUserDefault ),
.AxiAddrDomain ( Cfg.UsbAddrDomain ),
.AxiAddrMask ( Cfg.UsbAddrMask ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.axi_req_t ( axi_mst_req_t ),
Expand All @@ -1745,56 +1748,27 @@ module cheshire_soc import cheshire_pkg::*; #(
.dma_req_o ( axi_in_req[AxiIn.new_usb] ),
.dma_rsp_i ( axi_in_rsp[AxiIn.new_usb] ),
.intr_o ( intr.intn.usb ),
.phy_clk_i ( usb_clk_i ),
.phy_rst_ni ( usb_rst_ni ),
.phy_dm_i ( usb_dm_i ),
.phy_dm_o ( usb_dm_o ),
.phy_dm_oe_o ( usb_dm_oe_o ),
.phy_dp_i ( usb_dp_i ),
.phy_dp_o ( usb_dp_o ),
.phy_dp_oe_o ( usb_dp_oe_o )
.phy_clk_i ( usb_clk_i ),
.phy_rst_ni ( usb_rst_ni ),
.phy_dm_i ( usb_dm_i [NewUsbNumPorts-1:0]),
.phy_dm_o ( usb_dm_o [NewUsbNumPorts-1:0]),
.phy_dm_oe_o ( usb_dm_oe_o [NewUsbNumPorts-1:0]),
.phy_dp_i ( usb_dp_i [NewUsbNumPorts-1:0]),
.phy_dp_o ( usb_dp_o [NewUsbNumPorts-1:0]),
.phy_dp_oe_o ( usb_dp_oe_o [NewUsbNumPorts-1:0])
);

end else begin : gen_no_new_usb

assign usb_dm_o = '0;
assign usb_dm_oe_o = '0;
assign usb_dp_o = '0;
assign usb_dp_oe_o = '0;
assign usb_dm_o [NewUsbNumPorts-1:0] = '0;
assign usb_dm_oe_o [NewUsbNumPorts-1:0] = '0;
assign usb_dp_o [NewUsbNumPorts-1:0] = '0;
assign usb_dp_oe_o [NewUsbNumPorts-1:0] = '0;

assign intr.intn.new_usb = 0;

end

//if (Cfg.NewUsb) begin : gen_new_usb
//
//
// newusb_reg_top #(
// .reg_req_t ( reg_req_t ),
// .reg_rsp_t ( reg_rsp_t )
// ) i_regs (
// .clk_i,
// .rst_ni,
// .reg_req_i ( reg_out_req[RegOut.new_usb] ), //SW HCD
// .reg_rsp_o ( reg_out_rsp[RegOut.new_usb] ), //SW HCD
// .reg2hw ( /* NC */ ), //HW HC
// .hw2reg ( '0 ), //HW HC
// .devmode_i ( 1'b1 )
// );
//
// // DMA port tied-off
// assign axi_in_req[AxiIn.new_usb] = '0;
//
// // IRQ tied-off
// assign intr.intn.new_usb = '0;
//
//end else begin : gen_no_new_usb
//
// // tie-off other signals (USB PHY, IRQs)
// assign intr.intn.new_usb = '0;
//
//end

//////////////////
// Assertions //
//////////////////
Expand Down
24 changes: 13 additions & 11 deletions hw/newusb/new_usb_ohci.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -13,19 +13,18 @@
// because the package values need to influence the configuration inside newusb_regs.hjson.
package new_usb_ohci_pkg;

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[verible-verilog-lint] hw/newusb/new_usb_ohci.sv#L14 

Package declaration name must match the file name (ignoring optional "_pkg" file name suffix).  declaration: "new_usb_ohci_pkg" vs. basename(file): "new_usb_ohci" [Style: file-names] [package-filename]
Raw output 
message:"Package declaration name must match the file name (ignoring optional \"_pkg\" file name suffix).  declaration: \"new_usb_ohci_pkg\" vs. basename(file): \"new_usb_ohci\" [Style: file-names] [package-filename]"  location:{path:"hw/newusb/new_usb_ohci.sv"  range:{start:{line:14  column:9}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
//Supports between 1-15 ports
localparam int unsigned NumPhyPorts = 8;
//To Do: Overcurrent protection global/individual
localparam int unsigned NumPhyPorts = 2; //Todo: parametrize registers and everything else, currently only 2

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[verible-verilog-lint] hw/newusb/new_usb_ohci.sv#L16 

Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]"  location:{path:"hw/newusb/new_usb_ohci.sv"  range:{start:{line:16  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
// Todo: Overcurrent protection global/individual
// 0: off
// 1: global
// 2: individual
//To Do: Power switching protection global/individual
// Todo: Power switching protection global/individual
// 0: off
// 1: global
// 2: individual
//To Do: Fifodepth
//To Do: Usb Dmalength
//To Do: Beats per Dmalength
//To Do: words per Beat
// Todo: Interrupt routing
// Todo: Fifodepth, usbdmalength, etc.

endpackage

module new_usb_ohci import new_usb_ohci_pkg::*; #(
Expand Down Expand Up @@ -89,8 +88,11 @@ newusb_reg_top #(
// IRQ tied-off
assign intr_o = '0;

// assign usb_dm_o = '0;
// assign usb_dm_oe_o = '0;
// assign usb_dp_o = '0;
// assign usb_dp_oe_o = '0;
assign phy_dm_o = '0;
assign phy_dm_oe_o = '0;
assign phy_dp_o = '0;
assign phy_dp_oe_o = '0;

assign intr.intn.new_usb = 0;

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[verible-verilog-lint] hw/newusb/new_usb_ohci.sv#L97 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/newusb/new_usb_ohci.sv"  range:{start:{line:97  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:97  column:1}  end:{line:98}}  text:"\n"}
endmodule
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