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WIP: new_usb added (empty shell): x to z
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@fhaus1
fhaus1 committed Oct 30, 2024
1 parent 37d1254 commit 07bdcf6
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions hw/cheshire_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1698,11 +1698,11 @@ module cheshire_soc import cheshire_pkg::*; #(
.phy_clk_i ( usb_clk_i ),
.phy_rst_ni ( usb_rst_ni ),
.phy_dm_i ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'('b0), usb_dm_i [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),

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[verible-verilog-lint] hw/cheshire_soc.sv#L1700 

Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1700  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
.phy_dm_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'('bX), usb_dm_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),
.phy_dm_oe_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'('bX), usb_dm_oe_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),
.phy_dm_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'('bZ), usb_dm_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),

Check warning on line 1701 in hw/cheshire_soc.sv

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[verible-verilog-lint] hw/cheshire_soc.sv#L1701 

Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1701  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
.phy_dm_oe_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'('bZ), usb_dm_oe_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),

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[verible-verilog-lint] hw/cheshire_soc.sv#L1702 

Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1702  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
.phy_dp_i ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'('b0), usb_dp_i [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),

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[verible-verilog-lint] hw/cheshire_soc.sv#L1703 

Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1703  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
.phy_dp_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'('bX), usb_dp_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),
.phy_dp_oe_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'('bX), usb_dp_oe_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } )
.phy_dp_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'('bZ), usb_dp_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } ),

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[verible-verilog-lint] hw/cheshire_soc.sv#L1704 

Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1704  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
.phy_dp_oe_o ( {(SpinalUsbNumPorts_max-SpinalUsbNumPorts)'('bZ), usb_dp_oe_o [UsbNumPorts-1:UsbNumPorts-SpinalUsbNumPorts] } )

Check warning on line 1705 in hw/cheshire_soc.sv

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[verible-verilog-lint] hw/cheshire_soc.sv#L1705 

Line length exceeds max: 100; is: 133 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 133 [Style: line-length] [line-length]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1705  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
);

end else begin : gen_no_usb
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