fpga: Added ddr4 and vcu128 flow, added draft of Vivado IP simulation…

… flow

fpga: Added VIOs

Connect VIO-generated reset signal to dram wrapper

fpga: Support of zcu102

fpga: zcu102.xdc constraint file added

fpga: zcu102 changed phy and added firsts constraints

fpga: Switching to clk_wiz and xilinx.mk

Bender.yml

@@ -50,4 +50,6 @@ sources:
   - target: all(fpga, xilinx)
     files:
       - target/xilinx/src/fan_ctrl.sv
+      - target/xilinx/src/dram_wrapper.sv
+      - target/xilinx/src/phy_definitions.svh
       - target/xilinx/src/cheshire_top_xilinx.sv

cheshire.mk

@@ -55,7 +55,7 @@ chs-clean-deps:
 ######################
 
 CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= 86fa0ba
+CHS_NONFREE_COMMIT ?= cba93b7b90bb4a4080c099260a6518cb7b5c099d
 
 chs-nonfree-init:
 	git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree
@@ -154,10 +154,7 @@ chs-sim-all: $(CHS_ROOT)/target/sim/models/24FC1025.v
 chs-sim-all: $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 
 #############
-# FPGA Flow #
+# Emulation #
 #############
 
-$(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: Bender.yml
-	$(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 > $@
-
-chs-xilinx-all: $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl
+include $(CHS_ROOT)/target/xilinx/xilinx.mk

target/xilinx/README.md

@@ -0,0 +1,13 @@
+# VCU128 emulation
+
+```bash
+# Build the bitstream:
+make
+# Re-build the bitstream without
+# re-building the IPs:
+make rebuild-top
+# Simulate with the IPs
+# Note you need to generate the
+# Vivado IP models before
+make sim
+```

target/xilinx/constraints/cheshire.xdc

@@ -9,26 +9,29 @@
 # Global Settings #
 ###################
 
-# Testmode is set to 0 during normal use
-set_case_analysis 0 [get_ports test_mode_i]
-
 # Preserve the output mux of the clock divider
 set_property DONT_TOUCH TRUE [get_cells i_sys_clk_div/i_clk_bypass_mux]
 
-# The pin of which we get the 200 MHz single ended clock from the MIG
-set MIG_CLK_SRC {i_dram/ui_clk}
+# The net of which we get the 200 MHz single ended clock from the MIG
+set MIG_CLK_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_clock_out]]
+set MIG_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_sync_reset]]
+
+set SOC_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets rst_n]]
 
 #####################
 # Timing Parameters #
 #####################
 
-# 200 MHz FPGA diff clock
-set FPGA_TCK 5.0
+# 333 MHz (max) DRAM Axi clock
+set FPGA_TCK 3.0
+
+# 200 MHz DRAM Generated clock
+set DRAM_TCK 5.0
 
 # 50 MHz SoC clock
 set SOC_TCK 20.0
 
-# 10 MHz JTAG clock
+# 10 MHz (max) JTAG clock
 set JTAG_TCK 100.0
 
 # I2C High-speed mode is 3.2 Mb/s
@@ -42,8 +45,7 @@ set UART_IO_SPEED 200.0
 ##########
 
 # System Clock
-create_generated_clock -name clk_soc -source [get_pins $MIG_CLK_SRC] -divide_by 4 [get_pins i_sys_clk_div/i_clk_bypass_mux/i_BUFGMUX/O]
-
+create_generated_clock -name clk_soc -source $MIG_CLK_SRC -divide_by 4 [get_nets soc_clk]
 # JTAG Clock
 create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i]
 set_input_jitter clk_jtag 1.000
@@ -79,27 +81,8 @@ set_false_path -hold -from [get_ports jtag_trst_ni]
 # MIG #
 #######
 
-set_max_delay  -from [get_pins i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C] $FPGA_TCK
-set_false_path -hold -from [get_pins i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
-
-########
-# SPIM #
-########
-
-set_input_delay  -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}]
-set_input_delay  -max -clock clk_soc [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}]
-set_output_delay -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}]
-set_output_delay -max -clock clk_soc [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}]
-
-#######
-# I2C #
-#######
-
-set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}]
-set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}]
-
-set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}]
-set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}]
+set_max_delay  -from $MIG_RST_SRC $FPGA_TCK
+set_false_path -hold -from $MIG_RST_SRC
 
 ########
 # UART #
@@ -111,43 +94,22 @@ set_false_path -hold -from [get_ports uart_rx_i]
 set_max_delay [expr $UART_IO_SPEED * 0.35] -to [get_ports uart_tx_o]
 set_false_path -hold -to [get_ports uart_tx_o]
 
-#######
-# VGA #
-#######
-
-set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports vga*]
-set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports vga*]
-
-############
-# Switches #
-############
-
-set_input_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* test_mode_i}]
-set_input_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* test_mode_i}]
-
-set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports fan_pwm]
-set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports fan_pwm]
-
-set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* test_mode_i}]
-set_false_path -hold -from [get_ports {boot_mode* fan_sw* test_mode_i}]
-
-set_max_delay [expr 2 * $SOC_TCK] -to [get_ports fan_pwm]
-set_false_path -hold -to [get_ports fan_pwm]
-
 ########
 # CDCs #
 ########
 
 # cdc_fifo_gray: Disable hold checks, limit datapath delay and bus skew
-set_property KEEP_HIERARCHY SOFT [get_cells i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync]
-set_false_path -hold -through [get_pins -of_objects [get_cells i_axi_cdc_mig/i_axi_cdc_*]] -through [get_pins -of_objects [get_cells i_axi_cdc_mig/i_axi_cdc_*]]
-set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK
-set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_src_*/*i_sync/reg*/D] $FPGA_TCK
-set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK
+set_property KEEP_HIERARCHY SOFT [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync]
+set_false_path -hold -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]] -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]]
+set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK
+set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_src_*/*i_sync/reg*/D] $FPGA_TCK
+set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK
 
 ###################
 # Reset Generator #
 ###################
 
-set_max_delay -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] $SOC_TCK
-set_false_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}]
+set_max_delay -from $SOC_RST_SRC $SOC_TCK
+set_false_path -hold -from $SOC_RST_SRC
+
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_xlnx_clk_wiz/inst/clkin1_ibufds/O]

target/xilinx/constraints/genesys2.xdc

@@ -1,11 +1,61 @@
-#### This file is a general .xdc for the Genesys 2 Rev. H
-#### To use it in a project:
-#### - uncomment the lines corresponding to used pins
-#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+##############################
+# BOARD SPECIFIC CONSTRAINTS #
+##############################
+
+# Testmode is set to 0 during normal use
+set_case_analysis 0 [get_ports testmode_i]
+
+#######
+# VGA #
+#######
+
+set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports vga*]
+set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports vga*]
+
+############
+# Switches #
+############
+
+set_input_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* testmode_i}]
+set_input_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* testmode_i}]
+
+set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports fan_pwm]
+set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports fan_pwm]
+
+set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* testmode_i}]
+set_false_path -hold -from [get_ports {boot_mode* fan_sw* testmode_i}]
+
+set_max_delay [expr 2 * $SOC_TCK] -to [get_ports fan_pwm]
+set_false_path -hold -to [get_ports fan_pwm]
+
+########
+# SPIM #
+########
+
+set_input_delay  -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}]
+set_input_delay  -max -clock clk_soc [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}]
+set_output_delay -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}]
+set_output_delay -max -clock clk_soc [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}]
+
+#######
+# I2C #
+#######
+
+set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}]
+set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}]
+
+set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}]
+set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}]
+
+#################################################################################
+
+###############
+# ASSIGN PINS #
+###############
 
 ## Clock Signal
-set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
-set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
+# set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
+# set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
 
 ## Buttons
 #set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc
@@ -33,7 +83,7 @@ set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS12 } [get_ports { fan_sw
 set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS12 } [get_ports { fan_sw[2] }]; #IO_L19P_T3_A22_15 Sch=sw[4]
 set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS12 } [get_ports { fan_sw[3] }]; #IO_25_15 Sch=sw[5]
 #set_property -dict { PACKAGE_PIN P26   IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L10P_T1_D14_14 Sch=sw[6]
-set_property -dict { PACKAGE_PIN P27   IOSTANDARD LVCMOS33 } [get_ports { test_mode_i }]; #IO_L8P_T1_D11_14 Sch=sw[7]
+set_property -dict { PACKAGE_PIN P27   IOSTANDARD LVCMOS33 } [get_ports { testmode_i }]; #IO_L8P_T1_D11_14 Sch=sw[7]
 
 ## USB HIDs For Both Mouse and Keyboard
 #set_property -dict { PACKAGE_PIN AD23  IOSTANDARD LVCMOS33  PULLUP true } [get_ports { ps2_clk_0 }]; #IO_L12P_T1_MRCC_12 Sch=ps2_clk[0]