make: Introduce target lists for phonies

.gitignore

@@ -11,6 +11,9 @@ nonfree/
 # Dependency files
 .bender/
 
+# Phonies
+.phony/
+
 # Software build files
 *.bin
 *.dump

cheshire.mk

@@ -24,10 +24,6 @@ AXI_VGA_ROOT := $(shell $(BENDER) path axi_vga)
 
 REGTOOL ?= $(CHS_REG_DIR)/vendor/lowrisc_opentitan/util/regtool.py
 
-.PHONY: chs-all chs-nonfree-init chs-clean-deps chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-xilinx-all
-
-chs-all: chs-sw-all chs-hw-all chs-sim-all chs-xilinx-all
-
 ################
 # Dependencies #
 ################
@@ -85,29 +81,29 @@ $(CHS_ROOT)/hw/regs/axi_rt_reg_pkg.sv $(CHS_ROOT)/hw/regs/axi_rt_reg_top.sv: $(C
 CLINTCORES ?= 1
 include $(CLINTROOT)/clint.mk
 $(CLINTROOT)/.generated:
-	flock -x $@ $(MAKE) clint
+	flock -x $@ $(MAKE) clint && touch $@
 
 # OpenTitan peripherals
 include $(OTPROOT)/otp.mk
 $(OTPROOT)/.generated: $(CHS_ROOT)/hw/rv_plic.cfg.hjson
-	flock -x $@ sh -c "cp $< $(dir $@)/src/rv_plic/; $(MAKE) -j1 otp"
+	flock -x $@ sh -c "cp $< $(dir $@)/src/rv_plic/; $(MAKE) -j1 otp" && touch $@
 
 # AXI VGA
 include $(AXI_VGA_ROOT)/axi_vga.mk
 $(AXI_VGA_ROOT)/.generated:
-	flock -x $@ $(MAKE) axi_vga
+	flock -x $@ $(MAKE) axi_vga && touch $@
 
 # Custom serial link
 $(CHS_SLINK_DIR)/.generated: $(CHS_ROOT)/hw/serial_link.hjson
 	cp $< $(dir $@)/src/regs/serial_link_single_channel.hjson
-	flock -x $@ $(MAKE) -C $(CHS_SLINK_DIR) update-regs
+	flock -x $@ $(MAKE) -C $(CHS_SLINK_DIR) update-regs && touch $@
 
-chs-hw-all: $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv
-chs-hw-all: $(CHS_ROOT)/hw/regs/axi_rt_reg_pkg.sv $(CHS_ROOT)/hw/regs/axi_rt_reg_top.sv
-chs-hw-all: $(CLINTROOT)/.generated
-chs-hw-all: $(OTPROOT)/.generated
-chs-hw-all: $(AXI_VGA_ROOT)/.generated
-chs-hw-all: $(CHS_SLINK_DIR)/.generated
+PHONY_CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv
+PHONY_CHS_HW_ALL += $(CHS_ROOT)/hw/regs/axi_rt_reg_pkg.sv $(CHS_ROOT)/hw/regs/axi_rt_reg_top.sv
+PHONY_CHS_HW_ALL += $(CLINTROOT)/.generated
+PHONY_CHS_HW_ALL += $(OTPROOT)/.generated
+PHONY_CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated
+PHONY_CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated
 
 #####################
 # Generate Boot ROM #
@@ -125,7 +121,7 @@ $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.elf: $(CHS_ROOT)/hw/bootrom/cheshire_boo
 $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv: $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.bin $(CHS_ROOT)/util/gen_bootrom.py
 	$(CHS_ROOT)/util/gen_bootrom.py --sv-module cheshire_bootrom $< > $@
 
-chs-bootrom-all: $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.dump
+PHONY_CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.dump
 
 ##############
 # Simulation #
@@ -149,9 +145,9 @@ $(CHS_ROOT)/target/sim/models/24FC1025.v: Bender.yml | $(CHS_ROOT)/target/sim/mo
 	unzip -p 24xx1025_Verilog_Model.zip 24FC1025.v > $@
 	rm 24xx1025_Verilog_Model.zip
 
-chs-sim-all: $(CHS_ROOT)/target/sim/models/s25fs512s.v
-chs-sim-all: $(CHS_ROOT)/target/sim/models/24FC1025.v
-chs-sim-all: $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
+PHONY_CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/s25fs512s.v
+PHONY_CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/24FC1025.v
+PHONY_CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 
 #############
 # FPGA Flow #
@@ -160,4 +156,19 @@ chs-sim-all: $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: Bender.yml
 	$(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 > $@
 
-chs-xilinx-all: $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl
+PHONY_CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl
+
+#################################
+# Phonies (KEEP AT END OF FILE) #
+#################################
+
+.PHONY: chs-all chs-nonfree-init chs-clean-deps chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-xilinx-all
+
+PHONY_CHS_ALL += $(PHONY_CHS_SW_ALL) $(PHONY_CHS_HW_ALL) $(PHONY_CHS_SIM_ALL) $(PHONY_CHS_XILINX_ALL)
+
+chs-all:         $(PHONY_CHS_ALL)
+chs-sw-all:      $(PHONY_CHS_SW_ALL)
+chs-hw-all:      $(PHONY_CHS_HW_ALL)
+chs-bootrom-all: $(PHONY_CHS_BOOTROM_ALL)
+chs-sim-all:     $(PHONY_CHS_SIM_ALL)
+chs-xilinx-all:  $(PHONY_CHS_XILINX_ALL)

sw/sw.mk

@@ -28,10 +28,9 @@ CHS_SW_CCFLAGS ?= $(CHS_SW_FLAGS) -ggdb -mcmodel=medany -mexplicit-relocs -fno-b
 CHS_SW_LDFLAGS ?= $(CHS_SW_FLAGS) -nostartfiles -Wl,--gc-sections -Wl,-L$(CHS_SW_LD_DIR)
 CHS_SW_ARFLAGS ?= --plugin=$(CHS_SW_LTOPLUG)
 
-chs-sw-all: chs-sw-libs chs-sw-headers chs-sw-tests
+PHONY_CHS_SW_ALL += $(PHONY_CHS_SW_LIBS) $(PHONY_CHS_SW_HEADERS) $(PHONY_CHS_SW_TESTS)
 
 .PRECIOUS: %.elf %.dtb
-.PHONY: chs-sw-all chs-sw-libs chs-sw-headers chs-sw-tests
 
 ################
 # Dependencies #
@@ -62,7 +61,7 @@ $(CHS_SW_DIR)/lib/libcheshire.a: $(CHS_SW_LIB_SRCS_O)
 	rm -f $@
 	$(CHS_SW_AR) $(CHS_SW_ARFLAGS) -rcsv $@ $^
 
-chs-sw-libs: $(CHS_SW_LIBS)
+PHONY_CHS_SW_LIBS += $(CHS_SW_LIBS)
 
 #####################
 # Header generation #
@@ -86,7 +85,7 @@ $(eval $(call chs_sw_gen_hdr_rule,axi_rt,$(CHS_ROOT)/hw/regs/axi_rt_regs.hjson))
 
 # Generate headers for OT peripherals in the bendered repo itself
 CHS_SW_GEN_HDRS += $(OTPROOT)/.generated
-chs-sw-headers: $(CHS_SW_GEN_HDRS)
+PHONY_CHS_SW_HEADERS += $(CHS_SW_GEN_HDRS)
 
 ###############
 # Compilation #
@@ -163,4 +162,4 @@ CHS_SW_TEST_SPM_DUMP   	= $(CHS_SW_TEST_SRCS_S:.S=.spm.dump)  $(CHS_SW_TEST_SRCS
 CHS_SW_TEST_SPM_ROMH   	= $(CHS_SW_TEST_SRCS_S:.S=.rom.memh)  $(CHS_SW_TEST_SRCS_C:.c=.rom.memh)
 CHS_SW_TEST_SPM_GPTH   	= $(CHS_SW_TEST_SRCS_S:.S=.gpt.memh)  $(CHS_SW_TEST_SRCS_C:.c=.gpt.memh)
 
-chs-sw-tests: $(CHS_SW_TEST_DRAM_DUMP) $(CHS_SW_TEST_SPM_DUMP) $(CHS_SW_TEST_SPM_ROMH) $(CHS_SW_TEST_SPM_GPTH)
+PHONY_CHS_SW_TESTS += $(CHS_SW_TEST_DRAM_DUMP) $(CHS_SW_TEST_SPM_DUMP) $(CHS_SW_TEST_SPM_ROMH) $(CHS_SW_TEST_SPM_GPTH)