target/xilinx: Update default number of sync stages for intrs

pulp-platform · Aug 8, 2023 · 48c019b · 48c019b
1 parent 82aaa18
commit 48c019b
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv
@@ -78,6 +78,8 @@ module cheshire_top_xilinx
     NumCores          : 1,
     CoreMaxTxns       : 8,
     CoreMaxTxnsPerId  : 4,
+    // Interrupts
+    NumExtIntrSyncs   : 2,
     // Interconnect
     AddrWidth         : 48,
     AxiDataWidth      : 64,