target/verilator: First work on Verilator 5 support

.gitignore

@@ -26,28 +26,34 @@ site/
 *.dtb
 sw/deps/.patched
 
-# Test models
+# Simulation
 target/sim/models
 target/sim/dramsys
+target/sim**/*.log
+target/sim**/*.dasm
 
 # VSIM generated files
 target/sim/vsim/compile.*.tcl
-target/sim/vsim/*.log
 target/sim/vsim/modelsim.ini
 target/sim/vsim/transcript
 target/sim/vsim/vsim.wlf
+target/sim/vsim/*.vstf
 target/sim/vsim/work/
 
 # VCS generated files
 target/sim/vcs/compile.*.sh
-target/sim/vcs/*.log
 target/sim/vcs/AN.DB
 target/sim/vcs/simv*
 target/sim/vcs/csrc
 target/sim/vcs/ucli.key
 target/sim/vcs/work*
 target/sim/vcs/vc_hdrs.h
 
+# Verilator generated files
+target/sim/verilator/*.flist
+target/sim/verilator/obj_dir
+target/sim/verilator/V*
+
 # Xilinx generated files
 target/xilinx/build
 target/xilinx/out

Bender.lock

@@ -24,8 +24,8 @@ packages:
     - common_verification
     - tech_cells_generic
   axi_llc:
-    revision: 559bcbd09a5a884dbe31e2d72fd95d024e357f39
-    version: 0.2.1
+    revision: 59bb8a681347e1133f11a82190fbf4bc11900d9e
+    version: 0.2.2
     source:
       Git: https://github.com/pulp-platform/axi_llc.git
     dependencies:
@@ -85,8 +85,8 @@ packages:
     - common_cells
     - register_interface
   common_cells:
-    revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239
-    version: 1.33.0
+    revision: 9afda9abb565971649c2aa0985639c096f351171
+    version: 1.38.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:

Bender.yml

@@ -14,13 +14,13 @@ package:
 dependencies:
   apb_uart:                 { git: "https://github.com/pulp-platform/apb_uart.git",               version: 0.2.1  }
   axi:                      { git: "https://github.com/pulp-platform/axi.git",                    version: 0.39.6 }
-  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc.git",                version: 0.2.1  }
+  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc.git",                version: 0.2.2  }
   axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      version: 0.8.2  }
   axi_rt:                   { git: "https://github.com/pulp-platform/axi_rt.git",                 version: 0.0.0-alpha.9 }
   axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                version: 0.1.3  }
   clic:                     { git: "https://github.com/pulp-platform/clic.git",                   version: 2.0.0  }
   clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: 0.2.0  }
-  common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.33.0 }
+  common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.38.0 }
   common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
   cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: pulp-v1.0.0 }
   iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.6.3  }
@@ -45,10 +45,11 @@ sources:
   - hw/cheshire_pkg.sv
   - hw/cheshire_soc.sv
 
-  - target: any(simulation, test)
+  - target: any(verilator, simulation, test)
     files:
       - target/sim/models/s25fs512s.v
       - target/sim/models/24FC1025.v
+      - target/sim/src/jtag_test_simple.sv  # TODO: Upstream this
       - target/sim/src/vip_cheshire_soc.sv
       - target/sim/src/tb_cheshire_pkg.sv
       - target/sim/src/fixture_cheshire_soc.sv

cheshire.mk

@@ -6,14 +6,16 @@
 # Christopher Reinwardt <[email protected]>
 # Paul Scheffler <[email protected]>
 
-BENDER ?= bender
-VLOGAN ?= vlogan
+BENDER    ?= bender
+VLOGAN    ?= vlogan
+VERILATOR ?= oseda /scratch/vlbuild/install/bin/verilator
 
 # Caution: Questasim requires this to point to the *actual* compiler install path
 CXX_PATH := $(shell which $(CXX))
 
-VLOG_ARGS   ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps
-VLOGAN_ARGS ?= -kdb -nc -assert svaext +v2k -timescale=1ns/1ps
+VLOG_ARGS      ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps
+VLOGAN_ARGS    ?= -kdb -nc -assert svaext +v2k -timescale=1ns/1ps
+VERILATOR_ARGS ?= --binary -j 0 -Wall -Wno-fatal -Wno-BLKANDNBLK
 
 # Common Bender flags for Cheshire RTL
 CHS_BENDER_RTL_FLAGS ?= -t rtl -t cva6 -t cv64a6_imafdcsclic_sv39
@@ -155,25 +157,38 @@ $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh: $(CHS_ROOT)/Bender.yml
 	$(BENDER) script vcs -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOGAN_ARGS)" --vlogan-bin="$(VLOGAN)" > $@
 	chmod +x $@
 
-.PRECIOUS: $(CHS_ROOT)/target/sim/models
-$(CHS_ROOT)/target/sim/models:
-	mkdir -p $@
+$(CHS_ROOT)/target/sim/verilator/cheshire_soc.flist: $(CHS_ROOT)/Bender.yml
+	$(BENDER) script verilator $(CHS_BENDER_RTL_FLAGS) > $@
+	# TODO: Add verilator target for these upstream to avoid patch-in
+	echo '$(shell $(BENDER) path axi)/src/axi_sim_mem.sv' >> $@
+	echo '$(shell $(BENDER) path common_verification)/src/clk_rst_gen.sv' >> $@
+	echo '$(CHS_ROOT)/target/sim/src/elfloader.cpp' >> $@
+
+$(CHS_ROOT)/target/sim/verilator/V%: $(CHS_ROOT)/target/sim/verilator/cheshire_soc.flist
+	mkdir -p $(dir $@)
+	cd $(dir $@) && $(VERILATOR) $(VERILATOR_ARGS) -DASSERTS_OFF -f $< -top-module $*
+	ln -fs $(dir $@)/obj_dir/V$* $@
 
 # Download (partially non-free) simulation models from publically available sources;
 # by running these targets or targets depending on them, you accept this (see README.md).
-$(CHS_ROOT)/target/sim/models/s25fs512s.v: $(CHS_ROOT)/Bender.yml | $(CHS_ROOT)/target/sim/models
+$(CHS_ROOT)/target/sim/models/s25fs512s.v: $(CHS_ROOT)/Bender.yml
+	mkdir -p $(dir $@)
 	wget --no-check-certificate https://freemodelfoundry.com/fmf_vlog_models/flash/s25fs512s.v -O $@
 	touch $@
 
-$(CHS_ROOT)/target/sim/models/24FC1025.v: $(CHS_ROOT)/Bender.yml | $(CHS_ROOT)/target/sim/models
-	wget https://ww1.microchip.com/downloads/en/DeviceDoc/24xx1025_Verilog_Model.zip -o $@
-	unzip -p 24xx1025_Verilog_Model.zip 24FC1025.v > $@
-	rm 24xx1025_Verilog_Model.zip
+$(CHS_ROOT)/target/sim/models/24FC1025.v: $(CHS_ROOT)/Bender.yml
+	mkdir -p $(dir $@)
+	wget https://ww1.microchip.com/downloads/en/DeviceDoc/24xx1025_Verilog_Model.zip -O $@.zip
+	unzip -p $@.zip 24FC1025.v > $@
+	rm $@.zip
 
 CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/s25fs512s.v
 CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/24FC1025.v
 CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh
+CHS_SIM_ALL += $(CHS_ROOT)/target/sim/verilator/cheshire_soc.flist
+
+CHS_VERILATOR_ALL += $(CHS_ROOT)/target/sim/verilator/Vtb_cheshire_soc
 
 ###########
 # DRAMSys #
@@ -196,14 +211,15 @@ include $(CHS_ROOT)/target/xilinx/xilinx.mk
 
 CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL)
 
-chs-all:         $(CHS_ALL)
-chs-sw-all:      $(CHS_SW_ALL)
-chs-hw-all:      $(CHS_HW_ALL)
-chs-bootrom-all: $(CHS_BOOTROM_ALL)
-chs-sim-all:     $(CHS_SIM_ALL)
-chs-dramsys-all: $(CHS_DRAMSYS_ALL)
-chs-xilinx-all:  $(CHS_XILINX_ALL)
+chs-all:           $(CHS_ALL)
+chs-sw-all:        $(CHS_SW_ALL)
+chs-hw-all:        $(CHS_HW_ALL)
+chs-bootrom-all:   $(CHS_BOOTROM_ALL)
+chs-sim-all:       $(CHS_SIM_ALL)
+chs-verilator-all: $(CHS_VERILATOR_ALL)
+chs-dramsys-all:   $(CHS_DRAMSYS_ALL)
+chs-xilinx-all:    $(CHS_XILINX_ALL)
 
-CHS_PHONY += chs-all chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-dramsys-all chs-xilinx-all
+CHS_PHONY += chs-all chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-verilator-all chs-dramsys-all chs-xilinx-all
 
 .PHONY: $(CHS_PHONY)

target/sim/src/elfloader.cpp

@@ -150,7 +150,7 @@ int section_index = 0;
 extern "C" {
   char get_entry(long long *entry_ret);
   char get_section(long long *address_ret, long long *len_ret);
-  char read_section(long long address, const svOpenArrayHandle buffer, long long len);
+  char read_section_chunk(long long base, long long offset, char* buffer, long long len);
   char read_elf(const char *filename);
 }
 
@@ -187,28 +187,26 @@ extern "C" char get_section(long long *address_ret, long long *len_ret)
   }
 }
 
-extern "C" char read_section(long long address, const svOpenArrayHandle buffer, long long len)
+extern "C" char read_section_chunk(long long base, long long offset, char* buffer, long long len)
 {
-  // get actual pointer
-  char *buf = (char *) svGetArrayPtr(buffer);
-
-  // check that the address points to a section
-  if (!mems.count(address)) {
-    printf("[ELF] ERROR: No section found for address %p\n", address);
+  // check that the base address points to a section
+  if (!mems.count(base)) {
+    printf("[ELF] ERROR: No section found for base address %p\n", base);
     return -1;
   }
-
-  // copy array
-  long long int len_tmp = len;
-  for (auto &datum : mems.find(address)->second) {
-    if(len_tmp-- == 0){
-      printf("[ELF] ERROR: Copied 0x%lx bytes. Buffer is full but there is still data available.\n", len);
-      return -1;
-    }
 
-    *buf++ = datum;
+  // get memory vector for this section
+  auto mem = mems.find(base)->second;
+
+  // check for out-of-bounds access
+  if (offset < 0 || len < 0 || offset + len > mem.size()) {
+    printf("[ELF] ERROR: Offset %0p, length %d out of bounds for section at %p with length %d\n", offset, len, base, mem.size());
+    return -1;
   }
 
+  // copy data to SV array
+  std::copy(mem.begin() + offset, mem.begin() + offset + len, buffer);
+
   return 0;
 }