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vip: Simplify external port connection
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@paulsc96
paulsc96 committed Jul 19, 2023
1 parent 27f99b0 commit 586fbd9
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Showing 2 changed files with 63 additions and 48 deletions.
26 changes: 8 additions & 18 deletions target/sim/src/fixture_cheshire_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -148,27 +148,17 @@ module fixture_cheshire_soc;
// VIP //
///////////

AXI_BUS #(
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth-1 ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth )
) axi_unused_ext_mst ();

assign axi_unused_ext_mst.aw_valid = '0;
assign axi_unused_ext_mst.w_valid = '0;
assign axi_unused_ext_mst.b_ready = '1;
assign axi_unused_ext_mst.ar_valid = '0;
assign axi_unused_ext_mst.r_ready = '1;
axi_mst_req_t axi_slink_mst_req;
axi_mst_rsp_t axi_slink_mst_rsp;

assign axi_slink_ext_mst_req = '0;

vip_cheshire_soc #(
.DutCfg ( DutCfg ),
.axi_ext_llc_req_t ( axi_llc_req_t ),
.axi_ext_llc_rsp_t ( axi_llc_rsp_t )
) vip (
// The external axi driver is unconnected in cheshire
.axi_ext_mst (axi_unused_ext_mst),
.*
);
.axi_ext_llc_rsp_t ( axi_llc_rsp_t ),
.axi_ext_mst_req_t ( axi_mst_req_t ),
.axi_ext_mst_rsp_t ( axi_mst_rsp_t )
) vip (.*);

endmodule
85 changes: 55 additions & 30 deletions target/sim/src/vip_cheshire_soc.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
parameter cheshire_cfg_t DutCfg = '0,
parameter type axi_ext_llc_req_t = logic,
parameter type axi_ext_llc_rsp_t = logic,
parameter type axi_ext_mst_req_t = logic,
parameter type axi_ext_mst_rsp_t = logic,
// Timing
parameter time ClkPeriodSys = 5ns,
parameter time ClkPeriodJtag = 20ns,
Expand All @@ -31,6 +33,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
parameter int unsigned SlinkMaxWaitR = 5,
parameter int unsigned SlinkMaxWaitResp = 20,
parameter int unsigned SlinkBurstBytes = 1024,
parameter int unsigned SlinkMaxTxns = 32,
parameter int unsigned SlinkMaxTxnsPerId = 16,
parameter bit SlinkAxiDebug = 0,
// Derived Parameters; *do not override*
parameter int unsigned AxiStrbWidth = DutCfg.AxiDataWidth/8,
Expand All @@ -44,8 +48,9 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
// External AXI LLC (DRAM) port
input axi_ext_llc_req_t axi_llc_mst_req,
output axi_ext_llc_rsp_t axi_llc_mst_rsp,
// External virtual AXI ports
AXI_BUS.Slave axi_ext_mst,
// External serial link AXI port
input axi_ext_mst_req_t axi_slink_mst_req,
output axi_ext_mst_rsp_t axi_slink_mst_rsp,
// JTAG interface
output logic jtag_tck,
output logic jtag_trst_n,
Expand Down Expand Up @@ -549,31 +554,28 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
axi_mst_req_t slink_axi_mst_req, slink_axi_slv_req;
axi_mst_rsp_t slink_axi_mst_rsp, slink_axi_slv_rsp;

// AXI driver port
AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth-1 ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth )
) axi_drv_mst_dv (
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth )
) slink_mst_vip_dv (
.clk_i ( clk )
);

AXI_BUS #(
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth-1 ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth )
) axi_drv_mst ();

`AXI_ASSIGN (axi_drv_mst, axi_drv_mst_dv)

AXI_BUS #(
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth )
) slink_mst();
) slink_mst_ext(), slink_mst_vip(), slink_mst();

AXI_BUS #(
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth+1 ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth )
) slink_mst_mux();

AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
Expand All @@ -584,16 +586,10 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
.clk_i ( clk )
);

`AXI_ASSIGN_TO_REQ(slink_axi_mst_req, slink_mst)
`AXI_ASSIGN_FROM_RESP(slink_mst, slink_axi_mst_rsp)

`AXI_ASSIGN_FROM_REQ(slink_slv, slink_axi_slv_req)
`AXI_ASSIGN_TO_RESP(slink_axi_slv_rsp, slink_slv)

// Multiplex internal and external AXI requests
axi_mux_intf #(
.SLV_AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth-1 ),
.MST_AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ),
.SLV_AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ),
.MST_AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth+1 ),
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth ),
Expand All @@ -602,10 +598,39 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_i ( '0 ),
.slv ( {axi_drv_mst, axi_ext_mst} ),
.mst ( slink_mst )
.slv ( '{slink_mst_vip, slink_mst_ext} ),
.mst ( slink_mst_mux )
);

// Serialize away added AXI index bits
axi_id_serialize_intf #(
.AXI_SLV_PORT_ID_WIDTH ( DutCfg.AxiMstIdWidth+1 ),
.AXI_SLV_PORT_MAX_TXNS ( SlinkMaxTxns ),
.AXI_MST_PORT_ID_WIDTH ( DutCfg.AxiMstIdWidth ),
.AXI_MST_PORT_MAX_UNIQ_IDS ( 2**DutCfg.AxiMstIdWidth ),
.AXI_MST_PORT_MAX_TXNS_PER_ID ( SlinkMaxTxnsPerId ),
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth )
) i_axi_id_serialize_slink (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.slv ( slink_mst_mux ),
.mst ( slink_mst )
);

`AXI_ASSIGN (slink_mst_vip, slink_mst_vip_dv)

`AXI_ASSIGN_FROM_REQ(slink_mst_ext, axi_slink_mst_req)
`AXI_ASSIGN_TO_RESP(axi_slink_mst_rsp, slink_mst_ext)

`AXI_ASSIGN_TO_REQ(slink_axi_mst_req, slink_mst)
`AXI_ASSIGN_FROM_RESP(slink_mst, slink_axi_mst_rsp)

`AXI_ASSIGN_FROM_REQ(slink_slv, slink_axi_slv_req)
`AXI_ASSIGN_TO_RESP(slink_axi_slv_rsp, slink_slv)

// Mirror instance of serial link, reflecting another chip
serial_link #(
.axi_req_t ( axi_mst_req_t ),
.axi_rsp_t ( axi_mst_rsp_t ),
Expand Down Expand Up @@ -671,13 +696,13 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
typedef axi_test::axi_driver #(
.AW ( DutCfg.AddrWidth ),
.DW ( DutCfg.AxiDataWidth ),
.IW ( DutCfg.AxiMstIdWidth-1 ),
.IW ( DutCfg.AxiMstIdWidth ),
.UW ( DutCfg.AxiUserWidth ),
.TA ( ClkPeriodSys * TAppl ),
.TT ( ClkPeriodSys * TTest )
) slink_axi_driver_t;

slink_axi_driver_t slink_axi_driver = new (axi_drv_mst_dv);
slink_axi_driver_t slink_axi_driver = new (slink_mst_vip_dv);

initial begin
@(negedge rst_n);
Expand Down

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