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xilinx fix
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chaoqun-liang committed May 18, 2024
1 parent 6a47f10 commit 7a809f2
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Showing 2 changed files with 35 additions and 3 deletions.
30 changes: 30 additions & 0 deletions target/xilinx/constraints/genesys2.xdc
Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,36 @@ set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_d_i
set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset_o }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_sclk_o }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk

# Ethernet
set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
set_property -dict {PACKAGE_PIN A26 IOSTANDARD LVCMOS18} [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVCMOS18} [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
set_property -dict {PACKAGE_PIN G30 IOSTANDARD LVCMOS18} [get_ports { eth_txctl }]; #IO_L20P_T3_33 Sch=eth_tx_en
set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
set_property -dict {PACKAGE_PIN C27 IOSTANDARD LVCMOS18} [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
#set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
#set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports { eth_rst_n }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n

#############################################
# Ethernet Constraints for 1Gb/s
#############################################
# Modified for 125MHz receive clock
create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_rxck_IBUF]

set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_clkwiz/clk_125]]


# VGA Connector
set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_blue_o[0] }]; #IO_L22N_T3_12 Sch=vga_b[3]
set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_blue_o[1] }]; #IO_L22P_T3_12 Sch=vga_b[4]
Expand Down
8 changes: 5 additions & 3 deletions target/xilinx/src/cheshire_top_xilinx.sv
Original file line number Diff line number Diff line change
Expand Up @@ -125,6 +125,7 @@ module cheshire_top_xilinx (
wire soc_clk;
logic eth_clk_125;
logic eth_clk_90;
logic eth_clk_200;

IBUFDS #(
.IBUF_LOW_PWR ("FALSE")
Expand All @@ -138,7 +139,7 @@ module cheshire_top_xilinx (
.clk_in1 ( sys_clk ),
.reset ( '0 ),
.locked ( ),
.clk_200 ( ),
.clk_200 ( eth_clk_200 ),
.clk_50 ( soc_clk ),
.clk_125 ( eth_clk_125 ),
.clk_125_90 ( eth_clk_90 )
Expand Down Expand Up @@ -485,8 +486,9 @@ module cheshire_top_xilinx (
.i2c_scl_o ( i2c_scl_soc_out ),
.i2c_scl_i ( i2c_scl_soc_in ),
.i2c_scl_en_o ( i2c_scl_en ),
.eth_clk_125 ( eth_clk_125 ),
.eth_clk_90 ( eth_clk_90 ),
.eth_clk125_i ( eth_clk_125 ),
.eth_clk125q_i ( eth_clk_90 ),
.eth_clk200_i ( eth_clk_200 ),
.eth_rxck_i ( eth_rxck ),
.eth_rxd_i ( eth_rxd ),
.eth_rxctl_i ( eth_rxctl ),
Expand Down

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