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Merge pull request #74 from pulp-platform/bluewww/soc-reg-tests
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Improve SW helper functions and mixed fixes
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@alex96295
alex96295 authored Jun 29, 2023
2 parents 342ace2 + f4c5219 commit 7b4a200
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Showing 10 changed files with 530 additions and 56 deletions.
4 changes: 4 additions & 0 deletions carfield.mk
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Expand Up @@ -99,6 +99,10 @@ hw/regs/carfield_regs.hjson: hw/regs/carfield_regs.csv | venv
hw/regs/carfield_reg_pkg.sv hw/regs/carfield_reg_top.sv: hw/regs/carfield_regs.hjson | venv
$(VENV)/python utils/reggen/regtool.py -r $< --outdir $(dir $@)

.PHONY: sw/include/regs/soc_ctrl.h
sw/include/regs/soc_ctrl.h: hw/regs/carfield_regs.hjson | venv
$(VENV)/python utils/reggen/regtool.py -D $< > $@

## @section Carfield SoC HW Generation
.PHONY: regenerate_soc_regs
## Regenerate the toplevel SoC Control Register file from the CSV description of all registers in
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4 changes: 1 addition & 3 deletions hw/carfield.sv
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Expand Up @@ -63,8 +63,6 @@ module carfield
output logic jtag_safety_island_tdo_o,
// Secure Subsystem BOOT pins
input logic [1:0] bootmode_ot_i,
// unused by safety island -- tdo pad always out mode
output logic jtag_safe_isln_tdo_oe_o,
// Safety Island BOOT pins
input logic [1:0] bootmode_safe_isln_i,
// Host UART Interface
Expand Down Expand Up @@ -1548,7 +1546,7 @@ secure_subsystem_synth_wrap #(
.jtag_trst_n_i ( jtag_ot_trst_ni ),
.jtag_tdi_i ( jtag_ot_tdi_i ),
.jtag_tdo_o ( jtag_ot_tdo_o ),
.jtag_tdo_oe_o ( ),
.jtag_tdo_oe_o ( jtag_ot_tdo_oe_o),
// Asynch axi port
.async_axi_out_aw_data_o ( axi_mst_ext_aw_data [SecurityIslandMstIdx] ),
.async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [SecurityIslandMstIdx] ),
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25 changes: 17 additions & 8 deletions sw/include/car_memory_map.h
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Expand Up @@ -5,12 +5,15 @@
// Nicole Narr <[email protected]>
// Christopher Reinwardt <[email protected]>
// Paul Scheffler <[email protected]>
// Robert Balas <[email protected]>
// Alessandro Ottaviano <[email protected]>
//
// This header provides information defined by hardware parameters, such as
// the address map. In the future, it should be generated automatically as
// part of the SoC generation process.

#pragma once
#ifndef __CAR_MEMORY_MAP_H
#define __CAR_MEMORY_MAP_H

// Base addresses provided at link time
extern void *__base_l2;
Expand Down Expand Up @@ -46,20 +49,26 @@ extern void *__base_l2;
#define CAR_HYPERRAM_END_ADDR 0x80800000

// Peripheral devices
#define CAR_ETHERNET_BASE_ADDR 0x20000000
#define CAR_PERIPHS_BASE_ADDR 0x20001000
#define CAR_PERIPHS_BASE_ADDR 0x20000000

#define CAR_CAN_OFFSET 0x0000
#define CAR_SYSTEM_TIMER_OFFSET 0x3000
#define CAR_ADVANCED_TIMER_OFFSET 0x4000
#define CAR_WATCHDOG_TIMER_OFFSET 0x6000
#define CAR_HYPERBUS_CFG_OFFSET 0x8000
#define CAR_ETHERNET_OFFSET 0x0000
#define CAR_CAN_OFFSET 0x1000
#define CAR_SYSTEM_TIMER_OFFSET 0x4000
#define CAR_ADVANCED_TIMER_OFFSET 0x5000
#define CAR_WATCHDOG_TIMER_OFFSET 0x7000
#define CAR_HYPERBUS_CFG_OFFSET 0x9000
#define CAR_PAD_CFG_OFFSET 0xa000
#define CAR_SOC_CTRL_OFFSET 0x10000

#define CAR_ETHERNET_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_ETHERNET_OFFSET)
#define CAR_CAN_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_CAN_OFFSET)
#define CAR_SYSTEM_TIMER_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_SYSTEM_TIMER_OFFSET)
#define CAR_ADVANCED_TIMER_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_ADVANCED_TIMER_OFFSET)
#define CAR_WATCHDOG_TIMER_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_WATCHDOG_TIMER_OFFSET)
#define CAR_HYPERBUS_CFG_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_HYPERBUS_CFG_OFFSET)
#define CAR_PAD_CFG_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_PAD_CFG_OFFSET)
#define CAR_SOC_CTRL_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_SOC_CTRL_OFFSET)

#define CAR_MBOX_BASE_ADDR 0x40000000

#endif /* __CAR_MEMORY_MAP_H */
17 changes: 0 additions & 17 deletions sw/include/car_util.h
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This file was deleted.

76 changes: 76 additions & 0 deletions sw/include/csr.h
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@@ -0,0 +1,76 @@
// Copyright 2023 ETH Zurich and University of Bologna.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Robert Balas <[email protected]>
//

/* Description: CSR access macros
* Authors: Robert Balas ([email protected])
*/

#ifndef __CSR_H
#define __CSR_H

/* TODO: complete this */
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
#define CSR_MNXTI 0x345
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPADDR0 0x3b0
#define CSR_MHARTID 0xf14
#define CSR_MINTSTATUS 0x346
#define CSR_MINTTHRESH 0x347
#define CSR_MCLICBASE 0x350
#define MIE 8

#define __CSR_EXPAND(x) #x

#define csr_read(csr) \
({ \
register unsigned long __val; \
asm volatile("csrr %0, " __CSR_EXPAND(csr) \
: "=r"(__val) \
: \
: "memory"); \
__val; \
})

#define csr_write(csr, val) \
({ \
unsigned long __val = (unsigned long)(val); \
asm volatile("csrw " __CSR_EXPAND(csr) ", %0" \
: \
: "rK"(__val) \
: "memory"); \
})

/* I hope this properly does a memory barrier with the "memory" hint */
#define csr_read_clear(csr, val) \
({ \
unsigned long __val = (unsigned long)(val); \
asm volatile("csrrc %0, " __CSR_EXPAND(csr) ", %1" \
: "=r"(__val) \
: "rK"(__val) \
: "memory"); \
__val; \
})

#define csr_read_set(csr, val) \
({ \
unsigned long __val = (unsigned long)(val); \
asm volatile("csrrs %0, " __CSR_EXPAND(csr) ", %1" \
: "=r"(__val) \
: "rK"(__val) \
: "memory"); \
__val; \
})

#endif
94 changes: 94 additions & 0 deletions sw/include/io.h
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@@ -0,0 +1,94 @@
// Copyright 2023 ETH Zurich and University of Bologna.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Robert Balas <[email protected]>
//

/* Description: Memory mapped register I/O access
*/

#ifndef __IO_H
#define __IO_H

#include <stdint.h>


/* generic I/O write */
static inline void writeb(uint8_t val, uintptr_t addr)
{
asm volatile("sb %0, 0(%1)"
:
: "r"(val), "r"((volatile uint8_t *)addr)
: "memory");
}

static inline void writeh(uint16_t val, uintptr_t addr)
{
asm volatile("sh %0, 0(%1)"
:
: "r"(val), "r"((volatile uint16_t *)addr)
: "memory");
}

static inline void writew(uint32_t val, uintptr_t addr)
{
asm volatile("sw %0, 0(%1)"
:
: "r"(val), "r"((volatile uint32_t *)addr)
: "memory");
}

static inline void writed(uint64_t val, uintptr_t addr)
{
asm volatile("sd %0, 0(%1)"
:
: "r"(val), "r"((volatile uint64_t *)addr)
: "memory");
}

/* generic I/O read */
static inline uint8_t readb(const uintptr_t addr)
{
uint8_t val;

asm volatile("lb %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint8_t *)addr)
: "memory");
return val;
}

static inline uint16_t readh(const uintptr_t addr)
{
uint16_t val;

asm volatile("lh %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint16_t *)addr)
: "memory");
return val;
}

static inline uint32_t readw(const uintptr_t addr)
{
uint32_t val;

asm volatile("lw %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint32_t *)addr)
: "memory");
return val;
}

static inline uint64_t readd(const uintptr_t addr)
{
uint64_t val;

asm volatile("ld %0, 0(%1)"
: "=r"(val)
: "r"((const volatile uint64_t *)addr)
: "memory");
return val;
}
#endif
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