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fpga: Added ID serializer in dram_wrapper and changed a few xdc const…
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…raints
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CyrilKoe committed Aug 28, 2023
1 parent ef7d2f8 commit 8a9b83f
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Showing 5 changed files with 191 additions and 242 deletions.
9 changes: 4 additions & 5 deletions target/xilinx/constraints/cheshire.xdc
Original file line number Diff line number Diff line change
Expand Up @@ -20,11 +20,8 @@ set UART_IO_SPEED 200.0
# Clocks #
##########

# Clk_wiz clocks
create_clock -period 100 -name clk_10 [get_pins i_xlnx_clk_wiz/clk_10]
create_clock -period 50 -name clk_20 [get_pins i_xlnx_clk_wiz/clk_20]
create_clock -period 20 -name clk_50 [get_pins i_xlnx_clk_wiz/clk_50]
create_clock -period 10 -name clk_100 [get_pins i_xlnx_clk_wiz/clk_100]
# Clk_wiz clocks are named clk_(100,50,20,10)_xlnx_clk_wiz
# They are on pins : i_xlnx_clk_wiz/inst/mmcme4_adv_inst/CLKOUT(0,1,2,3)

# System Clock
# [see in board.xdc]
Expand Down Expand Up @@ -85,6 +82,8 @@ set_false_path -hold -to [get_ports uart_tx_o]

# Disable hold checks
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}]
set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] -filter {NAME=~*serial_i}]

# src false path
set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}]
# dst false path
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19 changes: 11 additions & 8 deletions target/xilinx/constraints/vcu128.xdc
Original file line number Diff line number Diff line change
Expand Up @@ -10,19 +10,22 @@
set SYS_TCK 10
create_clock -period $SYS_TCK -name sys_clk [get_pins u_ibufg_sys_clk/O]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O]
set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk}

#############
# Mig clock #
#############

# Dram axi clock : 833ps * 4
set MIG_TCK 3.332
set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
create_clock -period $MIG_TCK -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
set_clock_groups -name dram_async -asynchronous -group {dram_axi_clk}
set_false_path -hold -through $MIG_RST
set_max_delay -through $MIG_RST $MIG_TCK
# Dram axi clock : 750ps * 4
set MIG_TCK 3
create_generated_clock -source [get_pins i_dram_wrapper/i_dram/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0] \
-divide_by 1 -add -master_clock mmcm_clkout0 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
# Aynch reset in
set MIG_RST_I [get_pin i_dram_wrapper/i_dram/inst/c0_ddr4_aresetn]
set_false_path -hold -setup -through $MIG_RST_I
# Synch reset out
set MIG_RST_O [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
set_false_path -hold -through $MIG_RST_O
set_max_delay -through $MIG_RST_O $MIG_TCK

########
# CDCs #
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