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hw: Add UNBENT bus error unit (#68)
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@micprog
micprog authored Sep 5, 2023
1 parent 6589e2c commit 91ea189
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Showing 5 changed files with 190 additions and 14 deletions.
12 changes: 10 additions & 2 deletions Bender.lock
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Expand Up @@ -69,8 +69,8 @@ packages:
- common_cells
- register_interface
common_cells:
revision: 0989ff73d0315922791bf42137c0ce0cbb4a76ca
version: 1.30.0
revision: 53b0b58af2db5bd3c850a7038fae170ed78326bb
version: 1.31.1
source:
Git: https://github.com/pulp-platform/common_cells.git
dependencies:
Expand Down Expand Up @@ -169,3 +169,11 @@ packages:
Git: https://github.com/pulp-platform/tech_cells_generic.git
dependencies:
- common_verification
unbent:
revision: 791420b326c6455595b4444c02f05f180b99dd06
version: 0.1.1
source:
Git: https://github.com/pulp-platform/unbent.git
dependencies:
- common_cells
- register_interface
1 change: 1 addition & 0 deletions Bender.yml
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Expand Up @@ -28,6 +28,7 @@ dependencies:
serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.0 }
clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 }
irq_router: { git: "https://github.com/pulp-platform/irq_router.git", rev: d1d3135 } # TODO: master commit; use next release once out
unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.1 }

export_include_dirs:
- hw/include
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27 changes: 16 additions & 11 deletions hw/cheshire_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,7 @@ package cheshire_pkg;
bit AxiRt;
bit Clic;
bit IrqRouter;
bit BusErr;
// Parameters for Debug Module
jtag_idcode_t DbgIdCode;
dw_bt DbgMaxReqs;
Expand Down Expand Up @@ -178,6 +179,7 @@ package cheshire_pkg;

// Defined interrupts
typedef struct packed {
logic [5:0] bus_err; // VGA, DMA, CVA6
logic [31:0] gpio;
logic spih_spi_event;
logic spih_error;
Expand Down Expand Up @@ -347,6 +349,7 @@ package cheshire_pkg;
aw_bt axirt;
aw_bt [15:0] clic;
aw_bt irq_router;
aw_bt bus_err;
aw_bt ext_base;
aw_bt num_out;
aw_bt num_rules;
Expand All @@ -359,17 +362,18 @@ package cheshire_pkg;
ret.map[0] = '{1, 'h0204_0000, 'h0208_0000};
ret.map[1] = '{2, 'h0400_0000, 'h0800_0000};
ret.map[2] = '{3, AmRegs, AmRegs + 'h1000};
if (cfg.Bootrom) begin i++; ret.bootrom = i; r++; ret.map[r] = '{i, AmBrom, AmBrom + 'h40000}; end
if (cfg.LlcNotBypass) begin i++; ret.llc = i; r++; ret.map[r] = '{i, AmLlc, AmLlc + 'h1000}; end
if (cfg.Uart) begin i++; ret.uart = i; r++; ret.map[r] = '{i, 'h0300_2000, 'h0300_3000}; end
if (cfg.I2c) begin i++; ret.i2c = i; r++; ret.map[r] = '{i, 'h0300_3000, 'h0300_4000}; end
if (cfg.SpiHost) begin i++; ret.spi_host = i; r++; ret.map[r] = '{i, 'h0300_4000, 'h0300_5000}; end
if (cfg.Gpio) begin i++; ret.gpio = i; r++; ret.map[r] = '{i, 'h0300_5000, 'h0300_6000}; end
if (cfg.SerialLink) begin i++; ret.slink = i; r++; ret.map[r] = '{i, AmSlink, AmSlink +'h1000}; end
if (cfg.Vga) begin i++; ret.vga = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end
if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h0300_8000, 'h0300_9000}; end
if (cfg.IrqRouter) begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end
if (cfg.Clic) begin
if (cfg.Bootrom) begin i++; ret.bootrom = i; r++; ret.map[r] = '{i, AmBrom, AmBrom + 'h40000}; end
if (cfg.LlcNotBypass) begin i++; ret.llc = i; r++; ret.map[r] = '{i, AmLlc, AmLlc + 'h1000}; end
if (cfg.Uart) begin i++; ret.uart = i; r++; ret.map[r] = '{i, 'h0300_2000, 'h0300_3000}; end
if (cfg.I2c) begin i++; ret.i2c = i; r++; ret.map[r] = '{i, 'h0300_3000, 'h0300_4000}; end
if (cfg.SpiHost) begin i++; ret.spi_host = i; r++; ret.map[r] = '{i, 'h0300_4000, 'h0300_5000}; end
if (cfg.Gpio) begin i++; ret.gpio = i; r++; ret.map[r] = '{i, 'h0300_5000, 'h0300_6000}; end
if (cfg.SerialLink) begin i++; ret.slink = i; r++; ret.map[r] = '{i, AmSlink, AmSlink +'h1000}; end
if (cfg.Vga) begin i++; ret.vga = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end
if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h0300_8000, 'h0300_9000}; end
if (cfg.BusErr) begin i++; ret.bus_err = i; r++; ret.map[r] = '{i, 'h0300_9000, 'h0300_a000}; end
if (cfg.IrqRouter) begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end
if (cfg.Clic) begin
for (int j = 0; j < cfg.NumCores; j++) begin
i++; ret.clic[j] = i; r++; ret.map[r] = '{i, 'h0800_0000 + j * 'h4_0000, 'h0800_0000 + (j + 1) * 'h4_0000};
end
Expand Down Expand Up @@ -507,6 +511,7 @@ package cheshire_pkg;
AxiRt : 0,
Clic : 0,
IrqRouter : 0,
BusErr : 1,
// Debug
DbgIdCode : CheshireIdCode,
DbgMaxReqs : 4,
Expand Down
162 changes: 162 additions & 0 deletions hw/cheshire_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -421,6 +421,69 @@ module cheshire_soc import cheshire_pkg::*; #(
.rsp_o ( reg_out_rsp[RegOut.err] )
);

reg_req_t [Cfg.NumCores+3-1:0] bus_err_req;
reg_rsp_t [Cfg.NumCores+3-1:0] bus_err_rsp;
logic [Cfg.NumCores-1:0][1:0] bus_err_cores;

if (Cfg.BusErr) begin : gen_bus_err_reg_demux
logic [$clog2(Cfg.NumCores+3)-1:0] bus_err_select;

// Addr map:
// 0300_9000-0300_9040: VGA [1]
// 0300_9040-0300_9080: DMA [2] (iDMA should support internal error handling)
// 0300_9080-0300_90C0: core0 [3]
// 0300_90C0-0300_9100: core1 [4]
// 0300_91XX-0300_91XX: corei [i+3]

logic [1:0] core_bus_err_intr;
assign intr.intn.bus_err[5:4] = core_bus_err_intr;

always_comb begin
bus_err_select = '0;
core_bus_err_intr = bus_err_cores[0];

case (reg_out_req[RegOut.bus_err].addr[11:6])
6'h0: bus_err_select = 1; // VGA
6'h1: bus_err_select = 2; // DMA
6'h2: bus_err_select = 3; // core0
default: bus_err_select = '0;
endcase
for (int i = 1; i < Cfg.NumCores; i++) begin
if (reg_out_req[RegOut.bus_err].addr[11:6] == i+2) begin
bus_err_select = i+3;
end
core_bus_err_intr[0] |= bus_err_cores[i][0];
core_bus_err_intr[1] |= bus_err_cores[i][1];
end
end

reg_demux #(
.NoPorts ( Cfg.NumCores+3 ), // VGA, DMA, CVA6, err
.req_t ( reg_req_t ),
.rsp_t ( reg_rsp_t )
) i_reg_demux (
.clk_i,
.rst_ni,
.in_select_i ( bus_err_select ),
.in_req_i ( reg_out_req[RegOut.bus_err] ),
.in_rsp_o ( reg_out_rsp[RegOut.bus_err] ),
.out_req_o ( bus_err_req ),
.out_rsp_i ( bus_err_rsp )
);

reg_err_slv #(
.DW ( 32 ),
.ERR_VAL ( 32'hBADCAB1E ),
.req_t ( reg_req_t ),
.rsp_t ( reg_rsp_t )
) i_bus_err_slv (
.req_i ( bus_err_req[0] ),
.rsp_o ( bus_err_rsp[0] )
);
end else begin : gen_no_bus_err
assign intr.intn.bus_err = '0;
end

// Connect external slaves
if (Cfg.RegExtNumSlv > 0) begin : gen_ext_reg_slv
assign reg_ext_slv_req_o = reg_out_req[RegOut.num_out-1:RegOut.ext_base];
Expand Down Expand Up @@ -616,6 +679,32 @@ module cheshire_soc import cheshire_pkg::*; #(
.axi_resp_i ( core_out_rsp )
);

if (Cfg.BusErr) begin : gen_cva6_bus_err
axi_err_unit_wrap #(
.AddrWidth ( Cfg.AddrWidth ),
.IdWidth ( Cva6IdWidth ),
.UserErrBits ( 0 ),
.UserErrBitsOffset ( 0 ),
.NumOutstanding ( Cfg.CoreMaxTxns ),
.NumStoredErrors ( 4 ),
.DropOldest ( 1'b0 ),
.axi_req_t ( axi_cva6_req_t ),
.axi_rsp_t ( axi_cva6_rsp_t ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t )
) i_cva6_err (
.clk_i,
.rst_ni,
.testmode_i ( test_mode_i ),
.axi_req_i ( core_out_req ),
.axi_rsp_i ( core_out_rsp ),
.err_irq_o ( bus_err_cores[i] ),
.reg_req_i ( bus_err_req[i+3] ),
.reg_rsp_o ( bus_err_rsp[i+3] )
);
end


// Generate CLIC for core if enabled
if (Cfg.Clic) begin : gen_clic

Expand Down Expand Up @@ -1438,6 +1527,42 @@ module cheshire_soc import cheshire_pkg::*; #(
.axi_slv_rsp_o ( dma_cut_rsp )
);

if (Cfg.BusErr) begin : gen_dma_bus_err
axi_err_unit_wrap #(
.AddrWidth ( Cfg.AddrWidth ),
.IdWidth ( Cfg.AxiMstIdWidth ),
.UserErrBits ( 0 ),
.UserErrBitsOffset ( 0 ),
.NumOutstanding ( Cfg.CoreMaxTxns ),
.NumStoredErrors ( 4 ),
.DropOldest ( 1'b0 ),
.axi_req_t ( axi_mst_req_t ),
.axi_rsp_t ( axi_mst_rsp_t ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t )
) i_dma_err (
.clk_i,
.rst_ni,
.testmode_i ( test_mode_i ),
.axi_req_i ( axi_in_req[AxiIn.dma] ),
.axi_rsp_i ( axi_in_rsp[AxiIn.dma] ),
.err_irq_o ( intr.intn.bus_err[3:2] ),
.reg_req_i ( bus_err_req[2] ),
.reg_rsp_o ( bus_err_rsp[2] )
);
end
end else if (Cfg.BusErr) begin : gen_dma_err_slv

assign intr.intn.bus_err[3:2] = '0;
reg_err_slv #(
.DW ( 32 ),
.ERR_VAL ( 32'hBADCAB1E ),
.req_t ( reg_req_t ),
.rsp_t ( reg_rsp_t )
) i_dma_err_slv (
.req_i ( bus_err_req[2] ),
.rsp_o ( bus_err_rsp[2] )
);
end

///////////////////
Expand Down Expand Up @@ -1581,6 +1706,31 @@ module cheshire_soc import cheshire_pkg::*; #(
.blue_o ( vga_blue_o )
);

if (Cfg.BusErr) begin : gen_vga_bus_err
axi_err_unit_wrap #(
.AddrWidth ( Cfg.AddrWidth ),
.IdWidth ( Cfg.AxiMstIdWidth ),
.UserErrBits ( 0 ),
.UserErrBitsOffset ( 0 ),
.NumOutstanding ( Cfg.CoreMaxTxns ),
.NumStoredErrors ( 4 ),
.DropOldest ( 1'b0 ),
.axi_req_t ( axi_mst_req_t ),
.axi_rsp_t ( axi_mst_rsp_t ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t )
) i_vga_err (
.clk_i,
.rst_ni,
.testmode_i ( test_mode_i ),
.axi_req_i ( axi_in_req[AxiIn.vga] ),
.axi_rsp_i ( axi_in_rsp[AxiIn.vga] ),
.err_irq_o ( intr.intn.bus_err[1:0] ),
.reg_req_i ( bus_err_req[1] ),
.reg_rsp_o ( bus_err_rsp[1] )
);
end

end else begin : gen_no_vga

assign vga_hsync_o = 0;
Expand All @@ -1589,6 +1739,18 @@ module cheshire_soc import cheshire_pkg::*; #(
assign vga_green_o = '0;
assign vga_blue_o = '0;

if (Cfg.BusErr) begin : gen_vga_err_slv
assign intr.intn.bus_err[1:0] = '0;
reg_err_slv #(
.DW ( 32 ),
.ERR_VAL ( 32'hBADCAB1E ),
.req_t ( reg_req_t ),
.rsp_t ( reg_rsp_t )
) i_vga_err_slv (
.req_i ( bus_err_req[3] ),
.rsp_o ( bus_err_rsp[3] )
);
end
end

//////////////////
Expand Down
2 changes: 1 addition & 1 deletion hw/rv_plic.cfg.hjson
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Expand Up @@ -7,7 +7,7 @@
{
instance_name: "rv_plic",
param_values: {
src: 51,
src: 57,
target: 2, // We need *two targets* per hart: M and S modes
prio: 7,
nonstd_regs: 0 // Do *not* include these: MSIPs are not used and we use a 64 MiB address space
Expand Down

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