hw: Expose NumExtIntrSyncs as design parameter (#64)

* hw: Expose `NumExtIntrSyncs` as design parameter * target/xilinx: Update default number of sync stages for intrs
pulp-platform · Aug 8, 2023 · 97662be · 97662be
1 parent 44ad673
commit 97662be
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Showing 3 changed files with 5 additions and 2 deletions.
diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
@@ -79,6 +79,7 @@ package cheshire_pkg;
     byte_bt NumExtOutIntrTgts;
     shrt_bt NumExtOutIntrs;
     shrt_bt ClicIntCtlBits;
+    shrt_bt NumExtIntrSyncs;
     // AXI parameters
     aw_bt   AddrWidth;
     dw_bt   AxiDataWidth;
@@ -217,7 +218,6 @@ package cheshire_pkg;
   } cheshire_xeip_t;
 
   // Interrupt parameters
-  localparam int unsigned NumExtIntrSyncs = 2;
   localparam int unsigned NumIntIntrs     = $bits(cheshire_int_intr_t);
   localparam int unsigned NumIrqCtxts     = $bits(cheshire_xeip_t);
   localparam int unsigned NumCoreIrqs     = $bits(cheshire_core_ip_t);
@@ -478,6 +478,7 @@ package cheshire_pkg;
     NumExtOutIntrTgts : 0,
     NumExtOutIntrs    : 0,
     ClicIntCtlBits    : ariane_pkg::ArianeDefaultConfig.CLICIntCtlBits,
+    NumExtIntrSyncs   : 2,
     // Interconnect
     AddrWidth         : 48,
     AxiDataWidth      : 64,

diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -150,7 +150,7 @@ module cheshire_soc import cheshire_pkg::*; #(
   // External interrupts must be synchronized to this domain
   for (genvar i = 0; i <= iomsb(Cfg.NumExtInIntrs); i++) begin : gen_ext_in_intr_syncs
     sync #(
-      .STAGES     ( NumExtIntrSyncs ),
+      .STAGES     ( Cfg.NumExtIntrSyncs ),
       .ResetValue ( 1'b0 )
     ) i_ext_intr_sync (
       .clk_i,

diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv
@@ -78,6 +78,8 @@ module cheshire_top_xilinx
     NumCores          : 1,
     CoreMaxTxns       : 8,
     CoreMaxTxnsPerId  : 4,
+    // Interrupts
+    NumExtIntrSyncs   : 2,
     // Interconnect
     AddrWidth         : 48,
     AxiDataWidth      : 64,