Skip to content

Commit

Permalink
Adapt CVA6 to CLIC
Browse files Browse the repository at this point in the history
  • Loading branch information
@ezelioli
ezelioli committed Oct 23, 2024
1 parent ff00cc8 commit b997730
Show file tree
Hide file tree
Showing 2 changed files with 6 additions and 5 deletions.
5 changes: 3 additions & 2 deletions hw/cheshire_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -504,8 +504,9 @@ package cheshire_pkg;
ret.CachedRegionAddrBase = {AmSpm, cfg.LlcOutRegionStart, CieBase};
ret.CachedRegionLength = {SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength};
ret.DebugEn = 1;
//ret.RVSCLIC = cfg.Clic;
//ret.CLICNumInterruptSrc = NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs;
ret.RVSCLIC = cfg.Clic;
ret.CLICNumInterruptSrc = NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs;
// ret.CLICNumInterruptSrc = NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs;
// TODO: Should some things be removed from the main config?
// TODO: Should other things be added to the main config?
// TODO: Tune missing parameters of interest (esp. cache and interconnect) properly
Expand Down
6 changes: 3 additions & 3 deletions hw/cheshire_soc.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -617,7 +617,7 @@ module cheshire_soc import cheshire_pkg::*; #(
.ipi_i ( msip[i] ),
.time_irq_i ( mtip[i] ),
.debug_req_i ( dbg_int_req[i] ),
/*

Check warning on line 620 in hw/cheshire_soc.sv

View workflow job for this annotation

GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/cheshire_soc.sv#L620 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:620  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:620  column:1}  end:{line:621}}  text:"\n"}
.clic_irq_valid_i ( clic_irq_valid ),
.clic_irq_id_i ( clic_irq_id ),
.clic_irq_level_i ( clic_irq_level ),
Expand All @@ -626,7 +626,7 @@ module cheshire_soc import cheshire_pkg::*; #(
.clic_irq_ready_o ( clic_irq_ready ),
.clic_kill_req_i ( clic_irq_kill_req ),
.clic_kill_ack_o ( clic_irq_kill_ack ),
*/

Check warning on line 629 in hw/cheshire_soc.sv

View workflow job for this annotation

GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/cheshire_soc.sv#L629 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:629  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:629  column:1}  end:{line:630}}  text:"\n"}
.rvfi_probes_o ( ),
.cvxif_req_o ( ),
.cvxif_resp_i ( '0 ),
Expand Down Expand Up @@ -705,7 +705,7 @@ module cheshire_soc import cheshire_pkg::*; #(
assign clic_irq_id = '0;
assign clic_irq_level = '0;
assign clic_irq_shv = '0;
assign clic_irq_priv = riscv::priv_lvl_t'(0);
assign clic_irq_priv = riscv::priv_lvl_t'(2'b11);
assign clic_irq_kill_req = '0;

end
Expand Down

0 comments on commit b997730

Please sign in to comment.