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hw: Update axi_vga to fix performance issue (#113)
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* Bender.yml: Update dependencies

* axi_vga: Bump version to include an essential performance update

* Bender.yml: Switch to released version

* doc: Add new parameters, fix typo

---------

Co-authored-by: Paul Scheffler <[email protected]>
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@thommythomaso @paulsc96
thommythomaso and paulsc96 authored Mar 14, 2024
1 parent 3dca6cf commit f5b2823
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24 changes: 12 additions & 12 deletions Bender.lock
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Expand Up @@ -15,8 +15,8 @@ packages:
- apb
- register_interface
axi:
revision: fccffb5953ec8564218ba05e20adbedec845e014
version: 0.39.1
revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2
version: 0.39.2
source:
Git: https://github.com/pulp-platform/axi.git
dependencies:
Expand Down Expand Up @@ -44,17 +44,17 @@ packages:
- common_cells
- common_verification
axi_rt:
revision: 2be9d4028cd3fd6617a0302a53212495a4c4e3fa
version: 0.0.0-alpha.4
revision: 56074a195b1c8b05f4bdd73674e437bbcb35f2cd
version: 0.0.0-alpha.7
source:
Git: https://github.com/pulp-platform/axi_rt.git
dependencies:
- axi
- common_cells
- register_interface
axi_vga:
revision: 07be187d1e954d8090031b32d236ad76dc62ce45
version: 0.1.1
revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084
version: 0.1.3
source:
Git: https://github.com/pulp-platform/axi_vga.git
dependencies:
Expand All @@ -78,8 +78,8 @@ packages:
- common_cells
- register_interface
common_cells:
revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f
version: 1.32.0
revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239
version: 1.33.0
source:
Git: https://github.com/pulp-platform/common_cells.git
dependencies:
Expand Down Expand Up @@ -155,16 +155,16 @@ packages:
- common_cells
- common_verification
riscv-dbg:
revision: 138d74bcaa90c70180c12215db3776813d2a95f2
version: 0.8.0
revision: 358f90110220adf7a083f8b65d157e836d706236
version: 0.8.1
source:
Git: https://github.com/pulp-platform/riscv-dbg.git
dependencies:
- common_cells
- tech_cells_generic
serial_link:
revision: 77bec1aebd92b2ebea9962814f2370d5d48390c3
version: 1.1.0
revision: 5a25f5a71074f1ebb6de7b5280f2b16924bcc666
version: 1.1.1
source:
Git: https://github.com/pulp-platform/serial_link.git
dependencies:
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12 changes: 6 additions & 6 deletions Bender.yml
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Expand Up @@ -13,22 +13,22 @@ package:

dependencies:
apb_uart: { git: "https://github.com/pulp-platform/apb_uart.git", version: 0.2.1 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 }
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.2 }
axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.4 }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 }
axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.7 }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.3 }
clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 }
clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1.0.0 }
iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 }
irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 }
opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 }
riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.0 }
serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.0 }
riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 }
serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 }
unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 }

export_include_dirs:
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6 changes: 4 additions & 2 deletions docs/um/arch.md
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Expand Up @@ -225,6 +225,8 @@ The [VGA Controller](https://github.com/pulp-platform/axi_vga) enables the drawi
| -------------------------- | ------------ | ------------------------------------------------- |
| `Vga(Red|Green|Blue)Width` | `byte_bt` | Bit width of red, green, and blue output channels |
| `Vga(H|V)CountWidth` | `aw_bt` | Horizontal and vertical sync counter width |
| `VgaBufferDepth` | `dw_bt` | Depth of internal read data FIFO |
| `VgaMaxReadTxns` | `dw_bt` | Maximum number of outstanding reads |

### Serial Link

Expand All @@ -240,9 +242,9 @@ The [Serial Link](https://github.com/pulp-platform/serial_link) is a fully digit
| `SlinkTxAddrDomain` | `doub_bt` | Address domain to cast incoming requests into |
| `SlinkUserAmoBit` | `dw_bt` | AXI4 AMO user bit to set on incoming requests |

### DMA engine
### DMA Engine

The [iDMA engine](https://github.com/pulp-platform/iDMA) enables high-throughput asynchronous transfers between any two subordinate address ranges in the system. The hardware supports, if enabled, up to two-dimensional transfers directly in hardware. It exposes the following parameters:
The [iDMA Engine](https://github.com/pulp-platform/iDMA) enables high-throughput asynchronous transfers between any two subordinate address ranges in the system. The hardware supports, if enabled, up to two-dimensional transfers directly in hardware. It exposes the following parameters:

| Parameter | Type / Range | Description |
| ---------------------------- | ------------ | ------------------------------------------------- |
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4 changes: 4 additions & 0 deletions hw/cheshire_pkg.sv
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Expand Up @@ -161,6 +161,8 @@ package cheshire_pkg;
byte_bt VgaBlueWidth;
aw_bt VgaHCountWidth;
aw_bt VgaVCountWidth;
dw_bt VgaBufferDepth;
dw_bt VgaMaxReadTxns;
// Parameters for Serial Link
dw_bt SlinkMaxTxnsPerId;
dw_bt SlinkMaxUniqIds;
Expand Down Expand Up @@ -621,6 +623,8 @@ package cheshire_pkg;
VgaBlueWidth : 2,
VgaHCountWidth : 24, // TODO: Default is 32; is this needed?
VgaVCountWidth : 24, // TODO: See above
VgaBufferDepth : 16,
VgaMaxReadTxns : 24,
// Serial Link: map other chip's lower 32bit to 'h1_000_0000
SlinkMaxTxnsPerId : 4,
SlinkMaxUniqIds : 4,
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5 changes: 5 additions & 0 deletions hw/cheshire_soc.sv
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Expand Up @@ -1589,9 +1589,14 @@ module cheshire_soc import cheshire_pkg::*; #(
.VCountWidth ( Cfg.VgaVCountWidth ),
.AXIAddrWidth ( Cfg.AddrWidth ),
.AXIDataWidth ( Cfg.AxiDataWidth ),
.AXIIdWidth ( Cfg.AxiMstIdWidth ),
.AXIUserWidth ( Cfg.AxiUserWidth ),
.AXIStrbWidth ( AxiStrbWidth ),
.BufferDepth ( Cfg.VgaBufferDepth ),
.MaxReadTxns ( Cfg.VgaMaxReadTxns ),
.axi_req_t ( axi_mst_req_t ),
.axi_resp_t ( axi_mst_rsp_t ),
.axi_r_chan_t ( axi_mst_r_chan_t ),
.reg_req_t ( reg_req_t ),
.reg_resp_t ( reg_rsp_t )
) i_axi_vga (
Expand Down

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