Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

treewide: Add clic virtualization support #102

Draft
wants to merge 1 commit into
base: main
Choose a base branch
from
+26 −7
Draft

treewide: Add clic virtualization support #102

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 3 additions & 3 deletions Bender.lock
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -62,8 +62,8 @@ packages:
- common_cells
- register_interface
clic:
revision: 8ed76ffc779a435d0ed034f3068e4c3334fe2ecf
version: 2.0.0
revision: 94e2a77143053f1a2a72c88989616c89e05854fc
version: null
source:
Git: https://github.com/pulp-platform/clic.git
dependencies:
Expand Down Expand Up @@ -92,7 +92,7 @@ packages:
Git: https://github.com/pulp-platform/common_verification.git
dependencies: []
cva6:
revision: 9338c2ca7cf1a47aef54322f89ce867825c3c8d5
revision: 9b56333ed0976633c356db9303e3ecd353ab8dd4
version: null
source:
Git: https://github.com/pulp-platform/cva6.git
Expand Down
4 changes: 2 additions & 2 deletions Bender.yml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -18,11 +18,11 @@ dependencies:
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.2 }
axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.4 }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 }
clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 }
clic: { git: "https://github.com/pulp-platform/clic.git", rev: "94e2a77" } # branch: aottaviano/dev
clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1.0.0 }
cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: "9b56333" } # branch: aottaviano/vclic
iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 }
irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 }
opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 }
Expand Down
10 changes: 10 additions & 0 deletions hw/cheshire_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,11 @@ package cheshire_pkg;
byte_bt NumExtOutIntrTgts;
shrt_bt NumExtOutIntrs;
shrt_bt ClicIntCtlBits;
bit ClicUseSMode;
bit ClicUseUMode;
bit ClicUseVsMode;
bit ClicUseVsModePrio;
byte_bt ClicNumVsCtxts;
shrt_bt NumExtIntrSyncs;
// AXI parameters
aw_bt AddrWidth;
Expand Down Expand Up @@ -563,6 +568,11 @@ package cheshire_pkg;
NumExtOutIntrTgts : 0,
NumExtOutIntrs : 0,
ClicIntCtlBits : 8,
ClicUseSMode : 0,
ClicUseUMode : 0,
ClicUseVsMode : 0,
ClicUseVsModePrio : 0,
ClicNumVsCtxts : 0,
NumExtIntrSyncs : 2,
// Interconnect
AddrWidth : 48,
Expand Down
13 changes: 11 additions & 2 deletions hw/cheshire_soc.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -586,8 +586,10 @@ module cheshire_soc import cheshire_pkg::*; #(
logic clic_irq_valid, clic_irq_ready;
logic clic_irq_kill_req, clic_irq_kill_ack;
logic clic_irq_shv;
logic clic_irq_v;
logic [$clog2(NumClicIntrs)-1:0] clic_irq_id;
logic [7:0] clic_irq_level;
logic [5:0] clic_irq_vsid;
riscv::priv_lvl_t clic_irq_priv;

cva6 #(
Expand All @@ -613,6 +615,8 @@ module cheshire_soc import cheshire_pkg::*; #(
.clic_irq_level_i ( clic_irq_level ),
.clic_irq_priv_i ( clic_irq_priv ),
.clic_irq_shv_i ( clic_irq_shv ),
.clic_irq_v_i ( clic_irq_v ),
.clic_irq_vsid_i ( clic_irq_vsid ),
.clic_irq_ready_o ( clic_irq_ready ),
.clic_kill_req_i ( clic_irq_kill_req ),
.clic_kill_ack_o ( clic_irq_kill_ack ),
Expand Down Expand Up @@ -670,8 +674,11 @@ module cheshire_soc import cheshire_pkg::*; #(
.INTCTLBITS ( Cfg.ClicIntCtlBits ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.SSCLIC ( 1 ),
.USCLIC ( 0 )
.SSCLIC ( Cfg.ClicUseSMode ),
.USCLIC ( Cfg.ClicUseUMode ),
.VSCLIC ( Cfg.ClicUseVsMode ),
.VSPRIO ( Cfg.ClicUseVsModePrio ),
.N_VSCTXTS ( Cfg.ClicNumVsCtxts )
) i_clic (
.clk_i,
.rst_ni,
Expand All @@ -684,6 +691,8 @@ module cheshire_soc import cheshire_pkg::*; #(
.irq_level_o ( clic_irq_level ),
.irq_shv_o ( clic_irq_shv ),
.irq_priv_o ( clic_irq_priv ),
.irq_v_o ( clic_irq_v ),
.irq_vsid_o ( clic_irq_vsid ),
.irq_kill_req_o ( clic_irq_kill_req ),
.irq_kill_ack_i ( clic_irq_kill_ack )
);
Expand Down
Loading