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treewide: Add Ethernet peripheral #104

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treewide: Add Ethernet peripheral #104

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chaoqun-liang
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@chaoqun-liang chaoqun-liang commented Feb 22, 2024

@thommythomaso @alex96295

  • Dependencies update (axi-rt, idma)
  • idma regs update
  • pulp-ethernet integration

@chaoqun-liang chaoqun-liang changed the title idma and rt dependency update, minor fixes ethernet integration, idma and rt dependency update, minor fixes Feb 22, 2024
@alex96295 alex96295 changed the title ethernet integration, idma and rt dependency update, minor fixes treewide: Add Ethernet peripheral Feb 23, 2024
@alex96295 alex96295 self-requested a review February 23, 2024 07:56
Bender.lock Outdated
@@ -34,6 +34,13 @@ packages:
- common_verification
- register_interface
- tech_cells_generic
axi_mem_if:
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This is added because the dependency is in pulp-ethernet, please remove it as from my review (https://github.com/pulp-platform/pulp-ethernet/pull/3/files#r1500435712), it should not be needed.

SpiHost : 1,
Gpio : 1,
Dma : 1,
Dma : 0,
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I know this is WIP, but make sure you test correct working of the ethernet integration when the system DMA is enabled. Just a reminder :)

output logic eth_txck_o,
output logic [3:0] eth_txd_o,
output logic eth_txctl_o,
output logic eth_rstn_o,
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As the lint action on github suggests, there are some trailing spaces. Please remove trailing spaces before pushing

.reg_rsp_o ( reg_out_rsp[RegOut.ethernet] ) // req from cheshire def, but inside ethernet, it awaits for the type
);

end else begin : gen_no_ethernet
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@alex96295 alex96295 Feb 23, 2024

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Since the port is incoming into the crossbar, req is an input and resp is an output. Tie input to '0 and leave outputs floating

@@ -0,0 +1,72 @@
#include <stdio.h>
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Missing license + autorship

@@ -12,7 +12,7 @@ package tb_cheshire_pkg;
// A dedicated RT config
function automatic cheshire_cfg_t gen_cheshire_rt_cfg();
cheshire_cfg_t ret = DefaultCfg;
ret.AxiRt = 1;
ret.AxiRt = 0;
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It should work when AxiRt is enabled, same reminder as for the system DMA :)

@@ -12,7 +12,7 @@ set TESTBENCH tb_cheshire_soc
# Set voptargs only if not already set to make overridable.
# Default on fast simulation flags.
if {![info exists VOPTARGS]} {
set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +noacc=p+cheshire_soc. +acc=r+stream_xbar"
set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +acc=p+cheshire_soc. +acc=r+stream_xbar"
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Please do not upstream these changes, keep them local or set VOPTARGS when locally running the simulation :) let the default as is now

.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t )
) i_tx_eth_idma_wrap (
.clk_i,
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Suggestion: Update the ethernet here with the version with exposed clocks; this is important so that we can handle clock generation in Cheshire

@thommythomaso do you think we should handle clock generation for ethernet in cheshire, or expose these clocks also in cheshire and let the end user provide the correct clock? In the latter case, we can generate them in the cheshire testbench as for cheshire's main clock

Aquaticfuller pushed a commit that referenced this pull request Jul 16, 2024
@paulsc96 paulsc96 added astral and removed astral labels Sep 11, 2024
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3 participants