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GitHub Actions / verible-verilog-lint failed Apr 9, 2024 in 0s

reviewdog [verible-verilog-lint] report

reported by reviewdog 🐶

Findings (6)

hw/cheshire_soc.sv|32 col 34| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1306 col 50| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1316 col 15| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1325 col 44| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1331 col 44| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1336 col 101| Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]

Filtered Findings (0)

Annotations

Check warning on line 32 in hw/cheshire_soc.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/cheshire_soc.sv#L32

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:32  column:34}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:32  column:34}  end:{line:33}}  text:"  input  logic        eth_clk_90,\n"}

Check warning on line 1306 in hw/cheshire_soc.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/cheshire_soc.sv#L1306

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1306  column:50}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:1306  column:50}  end:{line:1307}}  text:"      .DataWidth           ( Cfg.AxiDataWidth  ),\n"}

Check warning on line 1316 in hw/cheshire_soc.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/cheshire_soc.sv#L1316

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1316  column:15}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:1316  column:15}  end:{line:1317}}  text:"      .rst_ni,\n"}

Check warning on line 1325 in hw/cheshire_soc.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/cheshire_soc.sv#L1325

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1325  column:44}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:1325  column:44}  end:{line:1326}}  text:"      .phy_resetn_o        ( eth_rstn_o  ),\n"}

Check warning on line 1331 in hw/cheshire_soc.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/cheshire_soc.sv#L1331

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1331  column:44}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:1331  column:44}  end:{line:1332}}  text:"      .phy_mdc_o           ( eth_mdc_o   ),\n"}

Check warning on line 1336 in hw/cheshire_soc.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/cheshire_soc.sv#L1336

Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1336  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}