Integrate Hyperbus peripheral #47

sermazz · 2024-10-04T18:15:22Z

This PR:

integrates the Hyperbus peripheral in the Chimera top RTL
integrates the HyperRAM VIP in the Chimera testbench
adds an addressability test for the Hyperbus and adds it to the CI
Config registers are still to be added add config registers to hyperbus #43
What address range should we use for the HyperRAM? https://github.com/pulp-platform/chimera/blob/smazzola/hyperbus/hw/chimera_pkg.sv#L128-L130

Lore0599

Overall LGTM

hw/chimera_top_wrapper.sv

sw/tests/testHyperbusAddr.c

hw/chimera_pkg.sv

sermazz · 2024-10-17T11:38:43Z

@Lore0599 @arpansur @Scheremo @adimauro-iis
CI is finally passing after the fixes on devel, we should now define the range we need for HyperRAM (https://github.com/pulp-platform/chimera/pull/47/files#diff-7310782802ac0d64363e8ceb9e90e54a5c0c858fc1e63688d48ad6964dd3fb4bR131). And also have a plan for #43.
If these are not blocking, we can merge.

Scheremo · 2024-10-17T12:26:18Z

@Lore0599 @arpansur @Scheremo @adimauro-iis CI is finally passing after the fixes on devel, we should now define the range we need for HyperRAM (https://github.com/pulp-platform/chimera/pull/47/files#diff-7310782802ac0d64363e8ceb9e90e54a5c0c858fc1e63688d48ad6964dd3fb4bR131). And also have a plan for #43. If these are not blocking, we can merge.

I think both are blocking but trivial to resolve. You can extend the register memory map range (0x3000_0000 - 0x4000_0000) contiguously with the config registers and map the hyperbus memory "somewhere reasonable" (why not 0x5000_0000?)

Lore0599 · 2024-10-21T12:32:33Z

bender.mk

@@ -8,4 +8,4 @@
 COMMON_TARGS ?=
 COMMON_TARGS += -t snitch_cluster -t cv32a6_convolve -t cva6 -t rtl

-SIM_TARGS = -t test -t sim
+SIM_TARGS = $(COMMON_TARGS) -t test -t sim


Why do you add here $(COMMON_TARGS)? Isn't the variable already used in sim.mk?

This also answers the other comment
Just a small modification to make (in my opinion) the flow clearer. At some point we'll have many targets in the bender.mk, e.g. SIM_TARGS, ASIC_TARGS, FPGA_XILING_TARGS, FPGA_whatever_TARGS, etc...
So I explicitly add $(COMMON_TARGS) (which is common to all of them) within all those other TARGS variables.
Previously, it was left to whoever wrote the independent target .mk (e.g., sim.mk, asic.mk, ...) to use both variables, as in: bender script vsim $(COMMON_TARGS) $(SIM_TARGS) [...].
But ultimately it's the same argument for bender so we might as well use this clearer form.

make sense, thanks

Lore0599 · 2024-10-21T12:38:29Z

target/sim/sim.mk

 $(CHIM_SIM_DIR)/vsim/compile.tcl: chs-hw-init snitch-hw-init
-	@bender script vsim $(COMMON_TARGS) $(SIM_TARGS) --vlog-arg="$(VLOG_ARGS)"> $@
+	@bender script vsim $(SIM_TARGS) --vlog-arg="$(CHIM_VLOG_ARGS)" > $@


Why did you remove $(COMMON_TARGS)?

Lore0599 · 2024-10-21T12:43:32Z

target/sim/src/vip_chimera_soc.sv

+        .UserPreload  (HypUserPreload),
+        .mem_file_name(HypUserPreloadMemFiles[i]),
+        .TimingModel  ("S27KS0641DPBHI020")
+      ) dut (


The Chimera instance inside fixture_chimera_soc.sv is already called DUT.

True but the hierarchy is different so no problem arises. Should I change it?

I think it's fine for now.

Scheremo

Looks mostly fine to me, some comments sprinkled throughout. Is there some consideration behind having two PHYs? I understand two endpoints (HyperRAM and HyperFlash), but that should only necessitate another CS pin.

Scheremo · 2024-10-17T12:43:18Z

Bender.yml

  - hw/chimera_top_wrapper.sv

  - target: any(simulation, test)
    files:
+      - target/sim/models/s27ks0641/s27ks0641.v


Is this included in Cheshire?

Scheremo · 2024-10-17T12:48:34Z

hw/chimera_top_wrapper.sv


 module chimera_top_wrapper
  import cheshire_pkg::*;
  import chimera_pkg::*;
  import chimera_reg_pkg::*;
 #(
-  parameter int unsigned SelectedCfg = 0
+  parameter int unsigned SelectedCfg = 0,
+  parameter int unsigned HypNumPhys  = 2,


Does this correspond to 2 PHYs? In this case I think a smarter default is 1 PHY.

Scheremo · 2024-10-22T14:38:15Z

hw/chimera_pkg.sv

+  localparam byte_bt HyperbusIdx = MemIslandIdx + 1;
+  localparam doub_bt HyperbusRegionStart = 64'h5000_0000;
+  //TODO(smazzola): Correct size of HyperRAM?
+  localparam doub_bt HyperbusRegionEnd = HyperbusRegionStart + 64'h0800_0000;


I think after our discussion last week, we can extend the region size of 64'h1000_0000

Scheremo · 2024-10-22T14:39:16Z

hw/chimera_top_wrapper.sv

+    .RstChipBase     (ChsCfg.LlcOutRegionStart),
+    .RstChipSpace    (HypNumPhys * HypNumChips * 'h800_0000),


Not sure this is correct, can you comment?

Scheremo · 2024-10-22T14:41:18Z

target/sim/src/vip_chimera_soc.sv

+        .UserPreload  (HypUserPreload),
+        .mem_file_name(HypUserPreloadMemFiles[i]),
+        .TimingModel  ("S27KS0641DPBHI020")
+      ) dut (


I think it's fine for now.

sermazz requested review from Scheremo and adimauro-iis October 4, 2024 18:15

sermazz changed the base branch from main to devel October 4, 2024 18:17

sermazz force-pushed the smazzola/hyperbus branch 5 times, most recently from 19cbd63 to d1090d3 Compare October 7, 2024 12:02

Lore0599 reviewed Oct 7, 2024

View reviewed changes

hw/chimera_top_wrapper.sv Outdated Show resolved Hide resolved

sw/tests/testHyperbusAddr.c Outdated Show resolved Hide resolved

hw/chimera_pkg.sv Show resolved Hide resolved

hw/chimera_pkg.sv Outdated Show resolved Hide resolved

sermazz force-pushed the smazzola/hyperbus branch from e8e14e2 to a91fe71 Compare October 8, 2024 09:55

sermazz changed the title ~~Integrate Hyperbus peripheral and test infrastructure~~ Integrate Hyperbus integration + stack pointer fix Oct 8, 2024

sermazz force-pushed the smazzola/hyperbus branch from 5f569cd to d1090d3 Compare October 8, 2024 11:17

sermazz changed the title ~~Integrate Hyperbus integration + stack pointer fix~~ Integrate Hyperbus peripheral Oct 8, 2024

sermazz force-pushed the smazzola/hyperbus branch from d1090d3 to abdb469 Compare October 8, 2024 11:52

arpansur and others added 2 commits October 17, 2024 12:21

Hw: Integrate HyperBus peripheral in Chimera top

46db4b5

Sim, Makefile: Integrate HyperRAM VIP in Chimera tb

d39690e

sermazz force-pushed the smazzola/hyperbus branch from abdb469 to 0c20226 Compare October 17, 2024 10:32

sermazz added 3 commits October 17, 2024 12:42

Sw: Create addressability test for Hyperbus

101184c

Hw: 🎨 Fix Hyperbus integration linting

fe9f02c

Tb: Fix HyperRAM sdf absolute path not working in CI

840a1dd

sermazz force-pushed the smazzola/hyperbus branch from 0c20226 to 840a1dd Compare October 17, 2024 11:10

sermazz requested a review from Lore0599 October 17, 2024 11:36

Lore0599 reviewed Oct 21, 2024

View reviewed changes

Scheremo reviewed Oct 22, 2024

View reviewed changes

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Integrate Hyperbus peripheral #47

Integrate Hyperbus peripheral #47

sermazz commented Oct 4, 2024 •

edited by Lore0599

Loading

Lore0599 left a comment

sermazz commented Oct 17, 2024

Scheremo commented Oct 17, 2024

Lore0599 Oct 21, 2024

sermazz Oct 21, 2024 •

edited

Loading

Lore0599 Oct 21, 2024

Lore0599 Oct 21, 2024

Lore0599 Oct 21, 2024

sermazz Oct 21, 2024

Scheremo Oct 22, 2024

Scheremo left a comment

Scheremo Oct 17, 2024

Scheremo Oct 17, 2024

Scheremo Oct 22, 2024

Scheremo Oct 22, 2024

Scheremo Oct 22, 2024

		.RstChipBase (ChsCfg.LlcOutRegionStart),
		.RstChipSpace (HypNumPhys * HypNumChips * 'h800_0000),

Integrate Hyperbus peripheral #47

Are you sure you want to change the base?

Integrate Hyperbus peripheral #47

Conversation

sermazz commented Oct 4, 2024 • edited by Lore0599 Loading

Lore0599 left a comment

Choose a reason for hiding this comment

sermazz commented Oct 17, 2024

Scheremo commented Oct 17, 2024

Choose a reason for hiding this comment

sermazz Oct 21, 2024 • edited Loading

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Scheremo left a comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

sermazz commented Oct 4, 2024 •

edited by Lore0599

Loading

sermazz Oct 21, 2024 •

edited

Loading