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fixup! Add fence.t (#14)
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paulsc96 committed Oct 18, 2024
1 parent 8fad130 commit 89a419a
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Showing 5 changed files with 14 additions and 13 deletions.
2 changes: 1 addition & 1 deletion core/cache_subsystem/std_nbdcache.sv
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Expand Up @@ -109,7 +109,7 @@ module std_nbdcache
cl_be_t be_ram;

// Busy signals
logic miss_handler_busy;
logic miss_handler_busy;
assign busy_o = |busy | miss_handler_busy;

// ------------------
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4 changes: 2 additions & 2 deletions core/cache_subsystem/wt_cache_subsystem.sv
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Expand Up @@ -115,8 +115,8 @@ module wt_cache_subsystem
dcache_req_t dcache_adapter;
dcache_rtrn_t adapter_dcache;

logic icache_busy;
logic dcache_busy;
logic icache_busy;
logic dcache_busy;

assign busy_o = dcache_busy | icache_busy;

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4 changes: 2 additions & 2 deletions core/cache_subsystem/wt_dcache.sv
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Expand Up @@ -128,10 +128,10 @@ module wt_dcache
wbuffer_t [ CVA6Cfg.WtDcacheWbufDepth-1:0] wbuffer_data;

// controllers -> management
logic [ NumPorts-2:0] ctrl_busy;
logic [ NumPorts-2:0] ctrl_busy;

// missunit -> management
logic missunit_busy;
logic missunit_busy;

assign busy_o = |ctrl_busy | missunit_busy | ~wbuffer_empty_o;

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3 changes: 2 additions & 1 deletion core/controller.sv
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Expand Up @@ -303,7 +303,8 @@ module controller
// ----------------------
always_comb begin
// halt the core if the fence is active
halt_o = halt_csr_i || halt_acc_i || (CVA6Cfg.DCacheType == config_pkg::WB && fence_active_q) || (fence_t_state_q != IDLE);;
halt_o = halt_csr_i || halt_acc_i ||(CVA6Cfg.DCacheType == config_pkg::WB && fence_active_q) ||
(fence_t_state_q != IDLE);
end

// ----------------------
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14 changes: 7 additions & 7 deletions core/csr_regfile.sv
Original file line number Diff line number Diff line change
Expand Up @@ -150,13 +150,13 @@ module csr_regfile
// L1 ICache Enable - CACHE
output logic icache_en_o,
// L1 DCache Enable - CACHE
output logic dcache_en_o,
output logic dcache_en_o,
// Padding time of fence.t relative to time interrupt - CONTROLLER
output logic [ 31:0] fence_t_pad_o,
output logic [31:0] fence_t_pad_o,
// Pad relative to selected source - CONTROLLER
output logic fence_t_src_sel_o,
output logic fence_t_src_sel_o,
// Largest recorded fence.t latency - CONTROLLER
input logic [ 31:0] fence_t_ceil_i,
input logic [31:0] fence_t_ceil_i,
// Accelerator memory consistent mode - ACC_DISPATCHER
output logic acc_cons_en_o,
// Performance Counter
Expand Down Expand Up @@ -973,9 +973,9 @@ module csr_regfile
(fence_t_ceil_i > fence_t_ceil_q[31:0]) ? fence_t_ceil_i : fence_t_ceil_q[31:0]
};

fiom_d = fiom_q;
dcache_d = dcache_q;
icache_d = icache_q;
fiom_d = fiom_q;
dcache_d = dcache_q;
icache_d = icache_q;
acc_cons_d = acc_cons_q;

if (CVA6Cfg.RVH) begin
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