Skip to content

Commit

Permalink
Std cache TB: adapt to new parametrization
Browse files Browse the repository at this point in the history
  • Loading branch information
@ezelioli
ezelioli committed Jul 11, 2024
1 parent 86e4d1d commit 9a030b9
Show file tree
Hide file tree
Showing 4 changed files with 66 additions and 32 deletions.
9 changes: 9 additions & 0 deletions Bender.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -299,6 +299,15 @@ sources:
- common/local/util/instr_trace_item.svh
- common/local/util/ex_trace_item.svh

- target: test
files:
- corev_apu/tb/tb_std_cache_subsystem/hdl/tb_std_cache_subsystem_pkg.sv
- corev_apu/tb/tb_std_cache_subsystem/hdl/amo_intf.sv
- corev_apu/tb/tb_std_cache_subsystem/hdl/dcache_intf.sv
- corev_apu/tb/tb_std_cache_subsystem/hdl/icache_intf.sv
- corev_apu/tb/tb_std_cache_subsystem/hdl/sram_intf.sv
- corev_apu/tb/tb_std_cache_subsystem/hdl/cva6_cache_dummy.sv

# TODO target define FPGA target + verification etc
# - target: test
# files:
Expand Down
62 changes: 43 additions & 19 deletions corev_apu/tb/tb_std_cache_subsystem/hdl/cva6_cache_dummy.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,15 +15,39 @@
module cva6
import ariane_pkg::*;
#(
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig,
parameter int unsigned AxiAddrWidth = ariane_axi::AddrWidth,
parameter int unsigned AxiDataWidth = ariane_axi::DataWidth,
parameter int unsigned AxiIdWidth = ariane_axi::IdWidth,
parameter type axi_ar_chan_t = ariane_axi::ar_chan_t,
parameter type axi_aw_chan_t = ariane_axi::aw_chan_t,
parameter type axi_w_chan_t = ariane_axi::w_chan_t,
parameter type axi_req_t = ariane_axi::req_t,
parameter type axi_rsp_t = ariane_axi::resp_t
parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
parameter int unsigned AxiAddrWidth = cva6_config_pkg::CVA6ConfigAxiAddrWidth,
parameter int unsigned AxiDataWidth = cva6_config_pkg::CVA6ConfigAxiDataWidth,
parameter int unsigned AxiIdWidth = cva6_config_pkg::CVA6ConfigAxiIdWidth,
parameter type axi_ar_chan_t = ariane_ace::ar_chan_t,
parameter type axi_aw_chan_t = ariane_ace::aw_chan_t,
parameter type axi_w_chan_t = ariane_ace::ariane_axi_w_chan_t,
parameter type axi_req_t = ariane_ace::req_t,
parameter type axi_rsp_t = ariane_ace::resp_t,
// RVFI
parameter type rvfi_probes_t = struct packed {
logic [TRANS_ID_BITS-1:0] issue_pointer;
logic [CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] commit_pointer;
logic flush_unissued_instr;
logic decoded_instr_valid;
logic flush;
logic decoded_instr_ack;
logic issue_instr_ack;
logic fetch_entry_valid;
logic [31:0] instruction;
logic is_compressed;
riscv::xlen_t rs1_forwarding;
riscv::xlen_t rs2_forwarding;
scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr;
exception_t ex_commit;
riscv::priv_lvl_t priv_lvl;
lsu_ctrl_t lsu_ctrl;
logic [((CVA6Cfg.CvxifEn || CVA6Cfg.RVV) ? 5 : 4)-1:0][riscv::XLEN-1:0] wbdata;
logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack;
logic [riscv::PLEN-1:0] mem_paddr;
logic debug_mode;
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata;
}
) (
input logic clk_i,
input logic rst_ni,
Expand All @@ -39,7 +63,7 @@ module cva6
input logic debug_req_i, // debug request (async)
// CLIC interface - unused
input logic clic_irq_valid_i, // CLIC interrupt request
input logic [$clog2(ArianeCfg.CLICNumInterruptSrc)-1:0] clic_irq_id_i, // interrupt source ID
input logic [$clog2(CVA6Cfg.CLICNumInterruptSrc)-1:0] clic_irq_id_i, // interrupt source ID
input logic [7:0] clic_irq_level_i, // interrupt level is 8-bit from CLIC spec
input riscv::priv_lvl_t clic_irq_priv_i, // CLIC interrupt privilege level
input logic clic_irq_shv_i, // selective hardware vectoring bit
Expand All @@ -48,7 +72,7 @@ module cva6
output logic clic_kill_ack_o, // kill acknowledge
// RISC-V formal interface port (`rvfi`):
// Can be left open when formal tracing is not needed.
output ariane_pkg::rvfi_port_t rvfi_o,
output rvfi_probes_t rvfi_probes_o,
output cvxif_pkg::cvxif_req_t cvxif_req_o,
input cvxif_pkg::cvxif_resp_t cvxif_resp_i,
// L15 (memory side)
Expand All @@ -64,10 +88,10 @@ module cva6
logic icache_en_csr;
logic icache_flush_ctrl_cache;
logic icache_miss_cache_perf;
icache_areq_i_t icache_areq_ex_cache;
icache_areq_o_t icache_areq_cache_ex;
icache_dreq_i_t icache_dreq_if_cache;
icache_dreq_o_t icache_dreq_cache_if;
icache_areq_t icache_areq_ex_cache;
icache_arsp_t icache_areq_cache_ex;
icache_dreq_t icache_dreq_if_cache;
icache_drsp_t icache_dreq_cache_if;

logic dcache_miss_cache_perf;
logic dcache_en_csr_nbdcache;
Expand Down Expand Up @@ -107,10 +131,10 @@ module cva6
// Cache Subsystem
// -------------------

if (DCACHE_TYPE == int'(cva6_config_pkg::WT)) begin : WT
if (DCACHE_TYPE == int'(config_pkg::WT)) begin : WT
// this is a cache subsystem that is compatible with OpenPiton
wt_cache_subsystem #(
.ArianeCfg ( ArianeCfg )
.CVA6Cfg ( CVA6Cfg )
) i_cache_subsystem (
// to D$
.clk_i ( clk_i ),
Expand Down Expand Up @@ -152,7 +176,7 @@ module cva6
// note: this only works with one cacheable region
// not as important since this cache subsystem is about to be
// deprecated
.ArianeCfg ( ArianeCfg ),
.CVA6Cfg ( CVA6Cfg ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiIdWidth ( AxiIdWidth ),
Expand Down Expand Up @@ -202,7 +226,7 @@ module cva6
// -------------------
// pragma translate_off
`ifndef VERILATOR
initial ariane_pkg::check_cfg(ArianeCfg);
initial config_pkg::check_cfg(CVA6Cfg);
`endif
// pragma translate_on

Expand Down
4 changes: 2 additions & 2 deletions corev_apu/tb/tb_std_cache_subsystem/hdl/icache_intf.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ interface icache_intf (
input logic clk
);
// request / response between CPU core and dcache
ariane_pkg::icache_dreq_i_t req;
ariane_pkg::icache_dreq_o_t resp;
ariane_pkg::icache_dreq_t req;
ariane_pkg::icache_drsp_t resp;

endinterface
23 changes: 12 additions & 11 deletions corev_apu/tb/tb_std_cache_subsystem/hdl/tb_std_cache_subsystem_pkg.sv
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
// Description: test utilities for the standard Ariane cache subsystem.
// main package definition
package tb_std_cache_subsystem_pkg;
import config_pkg::*;
import ariane_pkg::*;
import snoop_test::*;
import std_cache_pkg::*;
Expand Down Expand Up @@ -107,7 +108,7 @@ package tb_std_cache_subsystem_pkg;
endfunction


function automatic logic [63:0] get_rand_addr_from_cfg(ariane_cfg_t cfg);
function automatic logic [63:0] get_rand_addr_from_cfg(cva6_cfg_t cfg);
logic [63:0] start_addr, end_addr, range;
logic [31:0] addr_msb, addr_lsb;
int region;
Expand Down Expand Up @@ -179,9 +180,9 @@ package tb_std_cache_subsystem_pkg;
virtual amo_intf vif;
string name;
int verbosity;
ariane_cfg_t cfg;
cva6_cfg_t cfg;

function new (virtual amo_intf vif, ariane_cfg_t cfg, string name="amo_driver");
function new (virtual amo_intf vif, cva6_cfg_t cfg, string name="amo_driver");
this.vif = vif;
vif.req = '0;
this.name=name;
Expand Down Expand Up @@ -459,13 +460,13 @@ package tb_std_cache_subsystem_pkg;
class dcache_driver;

virtual dcache_intf vif;
ariane_cfg_t cfg;
cva6_cfg_t cfg;
string name;
int verbosity;
logic kill_req;
logic kill_armed;

function new (virtual dcache_intf vif, ariane_cfg_t cfg, string name="dcache_driver");
function new (virtual dcache_intf vif, cva6_cfg_t cfg, string name="dcache_driver");
this.vif = vif;
vif.req = '0;
vif.req.address_tag = $urandom;
Expand Down Expand Up @@ -927,13 +928,13 @@ package tb_std_cache_subsystem_pkg;
class icache_driver;

virtual icache_intf vif;
ariane_cfg_t cfg;
cva6_cfg_t cfg;
string name;
int verbosity;
logic en_random_req;
logic random_req_running;

function new (virtual icache_intf vif, ariane_cfg_t cfg, string name="icache_driver");
function new (virtual icache_intf vif, cva6_cfg_t cfg, string name="icache_driver");
this.vif = vif;
this.cfg = cfg;
vif.req = '0;
Expand Down Expand Up @@ -1190,7 +1191,7 @@ package tb_std_cache_subsystem_pkg;
virtual dcache_gnt_if gnt_vif;

string name;
ariane_cfg_t ArianeCfg;
cva6_cfg_t ArianeCfg;

// Cache model
cache_line_t [DCACHE_NUM_WORDS-1:0][DCACHE_SET_ASSOC-1:0] cache_status;
Expand All @@ -1208,7 +1209,7 @@ package tb_std_cache_subsystem_pkg;
function new (
virtual dcache_sram_if sram_vif,
virtual dcache_gnt_if gnt_vif,
ariane_cfg_t cfg,
cva6_cfg_t cfg,
string name="std_cache_scoreboard"
);
this.sram_vif = sram_vif;
Expand Down Expand Up @@ -3040,7 +3041,7 @@ package tb_std_cache_subsystem_pkg;
int verbosity;

string name;
ariane_cfg_t ArianeCfg;
cva6_cfg_t ArianeCfg;
bit enable_mem_check = 1;

mailbox #(amo_req) amo_req_mbox [NB_CORES];
Expand All @@ -3052,7 +3053,7 @@ package tb_std_cache_subsystem_pkg;
function new (
virtual sram_intf #(DCACHE_SET_ASSOC, SRAM_DATA_WIDTH, SRAM_NUM_WORDS) sram_vif [NB_CORES],
virtual dcache_sram_if dc_sram_vif [NB_CORES],
ariane_cfg_t cfg,
cva6_cfg_t cfg,
string name="std_dcache_checker"
);
this.name = name;
Expand Down

0 comments on commit 9a030b9

Please sign in to comment.