fence.t: Support 32-bit config

Signed-off-by: Nils Wistoff <[email protected]>

core/csr_regfile.sv

@@ -262,6 +262,7 @@ module csr_regfile
   riscv::xlen_t dcache_q, dcache_d;
   riscv::xlen_t icache_q, icache_d;
   riscv::xlen_t fence_t_pad_q, fence_t_pad_d;
+  riscv::xlen_t fence_t_sel_q, fence_t_sel_d;
   riscv::xlen_t fence_t_ceil_q, fence_t_ceil_d;
   riscv::xlen_t acc_cons_q, acc_cons_d;
 
@@ -799,6 +800,7 @@ module csr_regfile
         riscv::CSR_DCACHE: csr_rdata = dcache_q;
         riscv::CSR_ICACHE: csr_rdata = icache_q;
         riscv::CSR_FENCE_T_PAD: csr_rdata = fence_t_pad_q;
+        riscv::CSR_FENCE_T_SEL: csr_rdata = fence_t_sel_q;
         riscv::CSR_FENCE_T_CEIL: csr_rdata = fence_t_ceil_q;
         // custom (non RISC-V) accelerator memory consistency mode
         riscv::CSR_ACC_CONS: begin
@@ -936,10 +938,8 @@ module csr_regfile
     icache_d = icache_q;
     acc_cons_d = acc_cons_q;
     fence_t_pad_d = fence_t_pad_q;
-    fence_t_ceil_d = {
-      fence_t_ceil_q[63:32],
-      (fence_t_ceil_i > fence_t_ceil_q[31:0]) ? fence_t_ceil_i : fence_t_ceil_q[31:0]
-    };
+    fence_t_sel_d = fence_t_sel_q;
+    fence_t_ceil_d = fence_t_ceil_q;
 
     vsstatus_d = vsstatus_q;
     vstvec_d = vstvec_q;
@@ -1586,6 +1586,7 @@ module csr_regfile
         riscv::CSR_DCACHE: dcache_d = {{riscv::XLEN - 1{1'b0}}, csr_wdata[0]};  // enable bit
         riscv::CSR_ICACHE: icache_d = {{riscv::XLEN - 1{1'b0}}, csr_wdata[0]};  // enable bit
         riscv::CSR_FENCE_T_PAD: fence_t_pad_d = {{riscv::XLEN - 32{1'b0}}, csr_wdata[31:0]};
+        riscv::CSR_FENCE_T_SEL: fence_t_sel_d = {{riscv::XLEN - 1{1'b0}}, csr_wdata[31:0]};
         riscv::CSR_FENCE_T_CEIL: fence_t_ceil_d = {{riscv::XLEN - 31{1'b0}}, csr_wdata[32:0]};
         riscv::CSR_ACC_CONS: begin
           if (CVA6Cfg.EnableAccelerator) begin
@@ -2093,6 +2094,10 @@ module csr_regfile
       // actually return from debug mode
       debug_mode_d = 1'b0;
     end
+
+    // Update fence.t pad ceiling
+    if (fence_t_ceil_i > fence_t_ceil_q[31:0]) fence_t_ceil_d[31:0] = fence_t_ceil_i;
+
   end
 
   // ---------------------------
@@ -2398,7 +2403,7 @@ module csr_regfile
   assign dcache_en_o = dcache_q[0];
   assign acc_cons_en_o = CVA6Cfg.EnableAccelerator ? acc_cons_q[0] : 1'b0;
   assign fence_t_pad_o = fence_t_pad_q[31:0];
-  assign fence_t_src_sel_o = fence_t_ceil_q[32];
+  assign fence_t_src_sel_o = fence_t_sel_q[0];
 
   // determine if mprv needs to be considered if in debug mode
   assign mprv = (CVA6Cfg.DebugEn && debug_mode_q && !dcsr_q.mprven) ? 1'b0 : mstatus_q.mprv;
@@ -2443,6 +2448,7 @@ module csr_regfile
       mcountinhibit_q  <= '0;
       acc_cons_q       <= {{riscv::XLEN - 1{1'b0}}, CVA6Cfg.EnableAccelerator};
       fence_t_pad_q    <= {riscv::XLEN{1'b0}};
+      fence_t_sel_q    <= {riscv::XLEN{1'b0}};
       fence_t_ceil_q   <= {riscv::XLEN{1'b0}};
       // supervisor mode registers
       if (CVA6Cfg.RVS) begin
@@ -2528,6 +2534,7 @@ module csr_regfile
       mcountinhibit_q <= mcountinhibit_d;
       acc_cons_q      <= acc_cons_d;
       fence_t_pad_q   <= fence_t_pad_d;
+      fence_t_sel_q   <= fence_t_sel_d;
       fence_t_ceil_q  <= fence_t_ceil_d;
       // supervisor mode registers
       if (CVA6Cfg.RVS) begin

core/include/riscv_pkg.sv

@@ -646,7 +646,8 @@ package riscv;
     // Accelerator memory consistency (platform specific)
     CSR_ACC_CONS         = 12'h7C2,
     CSR_FENCE_T_PAD      = 12'h7C3,
-    CSR_FENCE_T_CEIL     = 12'h7C4,
+    CSR_FENCE_T_SEL      = 12'h7C4,
+    CSR_FENCE_T_CEIL     = 12'h7C5,
     // Triggers
     CSR_TSELECT          = 12'h7A0,
     CSR_TDATA1           = 12'h7A1,