std_cache: Decouple Valid/Dirty WE from Data WE

Signed-off-by: Nils Wistoff <[email protected]>
pulp-platform · Aug 11, 2023 · c6190e2 · c6190e2
1 parent 8cbdae7
commit c6190e2
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Showing 4 changed files with 16 additions and 10 deletions.
diff --git a/core/cache_subsystem/cache_ctrl.sv b/core/cache_subsystem/cache_ctrl.sv
@@ -296,10 +296,11 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
                     addr_o     = mem_req_q.index;
                     we_o       = 1'b1;
 
-                    be_o.vldrty = hit_way_q;
-
                     // set the correct byte enable
                     be_o.data[cl_offset>>3 +: 8]  = mem_req_q.be;
+                    for (int unsigned i = 0; i < DCACHE_SET_ASSOC; i++) begin
+                      if (hit_way_q[i]) be_o.vldrty[i] = '{valid: 1, dirty: be_o.data};
+                    end
                     data_o.data[cl_offset  +: 64] = mem_req_q.wdata;
                     // ~> change the state
                     data_o.dirty[cl_offset>>3 +: 8] = mem_req_q.be;

diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv
@@ -300,8 +300,11 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
                     addr_o       = mshr_q.addr[DCACHE_INDEX_WIDTH-1:0];
                     req_o        = evict_way_q;
                     we_o         = 1'b1;
-                    be_o         = '1;
-                    be_o.vldrty  = evict_way_q;
+                    be_o.tag     = '1;
+                    be_o.data    = '1;
+                    for (int unsigned i = 0; i < DCACHE_SET_ASSOC; i++) begin
+                      if (evict_way_q[i]) be_o.vldrty[i] = '1;
+                    end
                     data_o.tag   = mshr_q.addr[DCACHE_TAG_WIDTH+DCACHE_INDEX_WIDTH-1:DCACHE_INDEX_WIDTH];
                     data_o.data  = data_miss_fsm;
                     data_o.valid = 1'b1;
@@ -345,7 +348,9 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
                     we_o       = 1'b1;
                     data_o.valid = INVALIDATE_ON_FLUSH ? 1'b0 : 1'b1;
                     // invalidate
-                    be_o.vldrty = evict_way_q;
+                    for (int unsigned i = 0; i < DCACHE_SET_ASSOC; i++) begin
+                      if (evict_way_q[i]) be_o.vldrty[i] = '1;
+                    end
                     // go back to handling the miss or flushing, depending on where we came from
                     state_d = (state_q == WB_CACHELINE_MISS) ? MISS : FLUSH_REQ_STATUS;
                 end

diff --git a/core/cache_subsystem/std_nbdcache.sv b/core/cache_subsystem/std_nbdcache.sv
@@ -228,8 +228,8 @@ import std_cache_pkg::*;
       assign dirty_wdata[i]     = '{dirty: wdata_ram.dirty, valid: wdata_ram.valid};
       assign rdata_ram[i].dirty = dirty_rdata[i].dirty;
       assign rdata_ram[i].valid = dirty_rdata[i].valid;
-      assign be_valid_dirty_ram[i].valid = be_ram.vldrty[i];
-      assign be_valid_dirty_ram[i].dirty = be_ram.data & {(DCACHE_LINE_WIDTH/8){be_ram.vldrty[i]}};
+      assign be_valid_dirty_ram[i].valid = be_ram.vldrty[i].valid;
+      assign be_valid_dirty_ram[i].dirty = be_ram.vldrty[i].dirty;
     end
 
     sram #(

diff --git a/core/include/std_cache_pkg.sv b/core/include/std_cache_pkg.sv
@@ -74,9 +74,9 @@ package std_cache_pkg;
 
     // cache line byte enable
     typedef struct packed {
-        logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0]  tag;    // byte enable into tag array
-        logic [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data;   // byte enable into data array
-        logic [ariane_pkg::DCACHE_SET_ASSOC-1:0]        vldrty; // bit enable into state array (valid for a pair of dirty/valid bits)
+        logic    [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0]  tag;    // byte enable into tag array
+        logic    [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data;   // byte enable into data array
+        vldrty_t [ariane_pkg::DCACHE_SET_ASSOC-1:0]        vldrty; // bit enable into state array
     } cl_be_t;
 
     // convert one hot to bin for -> needed for cache replacement