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Added redundant MMU, (WIP: SPLIT signal for synthesis exploration)
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@OttG
OttG committed Aug 28, 2024
1 parent 584cd94 commit d666186
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Showing 2 changed files with 26 additions and 19 deletions.
5 changes: 5 additions & 0 deletions core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,11 @@ package cva6_config_pkg;

localparam CVA6ConfigRvfiTrace = 0;

`ifdef SPLIT
localparam RedSplitSize = `SPLIT;
`else
localparam RedSplitSize = 0;
`endif
localparam config_pkg::cva6_cfg_t cva6_cfg = '{
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
Expand Down
40 changes: 21 additions & 19 deletions core/mmu_sv39x4/cva6_mmu_sv39x4.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -139,9 +139,9 @@ module cva6_mmu_sv39x4

if (EccEnable) begin
localparam TLB_SIZE = 3 + $bits(riscv::pte_t) + $bits(riscv::pte_t) + $bits(riscv::GPLEN);
localparam LOG2_TLB = $log2(TLB_SIZE);
localparam LOG2_TLB = $clog2(TLB_SIZE);
localparam TLB_BUS_SIZE = 2**LOG2_TLB;
localparam BUS_SPLIT_SIZE = TLB_BUS_SIZE/(2**SPLIT_SIZE);
localparam BUS_SPLIT_SIZE = TLB_BUS_SIZE/(2**cva6_config_pkg::RedSplitSize);

typedef struct packed {
logic tlb_is_2M;
Expand All @@ -161,6 +161,7 @@ module cva6_mmu_sv39x4
riscv::pte_t [2:0] red_itlb_content;
logic [2:0][riscv::GPLEN-1:0] red_itlb_gpaddr;
tlb_bus_t [2:0] itlb_bus;
logic [TLB_BUS_SIZE-1:0] itlb_majority_helper;
tlb_bus_t itlb_majority;

logic [2:0] red_dtlb_is_2M;
Expand All @@ -170,16 +171,18 @@ module cva6_mmu_sv39x4
riscv::pte_t [2:0] red_dtlb_g_content;
logic [2:0][riscv::GPLEN-1:0] red_dtlb_gpaddr;
tlb_bus_t [2:0] dtlb_bus;
logic [TLB_BUS_SIZE-1:0] dtlb_majority_helper;
tlb_bus_t dtlb_majority;

for (genvar i=0; i<3; i++) begin
for (genvar i=0; i<3; i++) begin: gen_redundancy_bus
assign itlb_bus[i] = '{
padding: '0,
tlb_is_2M: red_itlb_is_2M[i],
tlb_is_1G: red_itlb_is_1G[i],
tlb_lu_hit: red_itlb_lu_hit[i],
tlb_g_content: red_itlb_g_content[i],
tlb_content: red_itlb_content[i]
tlb_content: red_itlb_content[i],
tlb_gpaddr: red_itlb_gpaddr[i]
};

assign dtlb_bus[i] = '{
Expand All @@ -188,21 +191,20 @@ module cva6_mmu_sv39x4
tlb_is_1G: red_dtlb_is_1G[i],
tlb_lu_hit: red_dtlb_lu_hit[i],
tlb_g_content: red_dtlb_g_content[i],
tlb_content: red_dtlb_content[i]
tlb_content: red_dtlb_content[i],
tlb_gpaddr: red_dtlb_gpaddr[i]
};
end

for (genvar i=0; i<3; i++) begin
for (genvar i=0; i<3; i++) begin: gen_redundancy_tlb
cva6_tlb_sv39x4 #(
.CVA6Cfg (CVA6Cfg),
.TLB_ENTRIES(INSTR_TLB_ENTRIES),
.ASID_WIDTH (ASID_WIDTH),
.VMID_WIDTH (VMID_WIDTH),
.EccEnable (EccEnable)
.VMID_WIDTH (VMID_WIDTH)
) i_itlb (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clear_i (clear_i),
.flush_i (flush_tlb_i),
.flush_vvma_i(flush_tlb_vvma_i),
.flush_gvma_i(flush_tlb_gvma_i),
Expand Down Expand Up @@ -233,12 +235,10 @@ module cva6_mmu_sv39x4
.CVA6Cfg (CVA6Cfg),
.TLB_ENTRIES(DATA_TLB_ENTRIES),
.ASID_WIDTH (ASID_WIDTH),
.VMID_WIDTH (VMID_WIDTH),
.EccEnable (EccEnable)
.VMID_WIDTH (VMID_WIDTH)
) i_dtlb (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clear_i (clear_i),
.flush_i (flush_tlb_i),
.flush_vvma_i(flush_tlb_vvma_i),
.flush_gvma_i(flush_tlb_gvma_i),
Expand Down Expand Up @@ -266,14 +266,16 @@ module cva6_mmu_sv39x4
);
end

for (genvar i=0; i<2**SPLIT_SIZE; i++) begin
for (genvar i=0; i<2**cva6_config_pkg::RedSplitSize; i++) begin: gen_word_voter
logic [BUS_SPLIT_SIZE-1:0] itlb_helper, dtlb_helper;

TMR_word_voter #(
.DataWidth (BUS_SPLIT_SIZE)
) i_TMR_word_voter_itlb (
.a_i (itlb_bus[0][BUS_SPLIT_SIZE*(i+1) - 1 : BUS_SPLIT_SIZE*i]),
.b_i (itlb_bus[1][BUS_SPLIT_SIZE*(i+1) - 1 : BUS_SPLIT_SIZE*i]),
.c_i (itlb_bus[2][BUS_SPLIT_SIZE*(i+1) - 1 : BUS_SPLIT_SIZE*i]),
.majority_o (itlb_majority[BUS_SPLIT_SIZE*(i+1) - 1 : BUS_SPLIT_SIZE*i]),
.majority_o (itlb_majority_helper[BUS_SPLIT_SIZE*(i+1) - 1 : BUS_SPLIT_SIZE*i]),
.error_o (),
.error_cba_o ()
);
Expand All @@ -284,19 +286,21 @@ module cva6_mmu_sv39x4
.a_i (dtlb_bus[0][BUS_SPLIT_SIZE*(i+1) - 1 : BUS_SPLIT_SIZE*i]),
.b_i (dtlb_bus[1][BUS_SPLIT_SIZE*(i+1) - 1 : BUS_SPLIT_SIZE*i]),
.c_i (dtlb_bus[2][BUS_SPLIT_SIZE*(i+1) - 1 : BUS_SPLIT_SIZE*i]),
.majority_o (dtlb_majority[BUS_SPLIT_SIZE*(i+1) - 1 : BUS_SPLIT_SIZE*i]),
.majority_o (dtlb_majority_helper[BUS_SPLIT_SIZE*(i+1) - 1 : BUS_SPLIT_SIZE*i]),
.error_o (),
.error_cba_o ()
);
end

assign itlb_majority = tlb_bus_t'(itlb_majority_helper);
assign itlb_content = itlb_majority.tlb_content;
assign itlb_g_content = itlb_majority.tlb_g_content;
assign itlb_gpaddr = itlb_majority.tlb_gpaddr;
assign itlb_is_2M = itlb_majority.tlb_is_2M;
assign itlb_is_1G = itlb_majority.tlb_is_1G;
assign itlb_lu_hit = itlb_majority.tlb_lu_hit;

assign dtlb_majority = tlb_bus_t'(dtlb_majority_helper);
assign dtlb_content = dtlb_majority.tlb_content;
assign dtlb_g_content = dtlb_majority.tlb_g_content;
assign dtlb_gpaddr = dtlb_majority.tlb_gpaddr;
Expand All @@ -308,8 +312,7 @@ module cva6_mmu_sv39x4
.CVA6Cfg (CVA6Cfg),
.TLB_ENTRIES(INSTR_TLB_ENTRIES),
.ASID_WIDTH (ASID_WIDTH),
.VMID_WIDTH (VMID_WIDTH),
.EccEnable (EccEnable)
.VMID_WIDTH (VMID_WIDTH)
) i_itlb (
.clk_i (clk_i),
.rst_ni (rst_ni),
Expand Down Expand Up @@ -344,8 +347,7 @@ module cva6_mmu_sv39x4
.CVA6Cfg (CVA6Cfg),
.TLB_ENTRIES(DATA_TLB_ENTRIES),
.ASID_WIDTH (ASID_WIDTH),
.VMID_WIDTH (VMID_WIDTH),
.EccEnable (EccEnable)
.VMID_WIDTH (VMID_WIDTH)
) i_dtlb (
.clk_i (clk_i),
.rst_ni (rst_ni),
Expand Down

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