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Update csr_regfile.sv
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ezelioli authored Mar 4, 2024
1 parent 5d5cac8 commit e604564
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3 changes: 3 additions & 0 deletions core/csr_regfile.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1085,6 +1085,9 @@ module csr_regfile
if (clic_mode_o) begin
vsintthresh_d.th = csr_wdata[7:0];
end
end else begin
update_access_exception = 1'b1;
end
end
riscv::CSR_VSTVEC: begin
if (CVA6Cfg.RVH) begin
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