Add CLIC support (#10)

* Add initial CLIC support

Co-authored-by: aottaviano <[email protected]>

* core: Fix propagation of CLIC configuration

* clic: Fix syntax, preserve old irq signals

* clic/ariane_testharness: Fix CVA6 portlist

* fixup! clic/ariane_testharness: Fix CVA6 portlist

* fixup! fixup! clic/ariane_testharness: Fix CVA6 portlist

* clic/ariane_testharness: Define `meip` and `seip`

* csr_regfile: Update `stvec` for CLIC

* csr_regfile: Write CLIC mode to `mtvec` only if en

Signed-off-by: Nils Wistoff <[email protected]>

* ci: Disable CLIC test

* csr_regfile: Add `sintstatus` and `sintthresh` CSR

* clic/id_stage: Add lower priv irq accept logic

* fixup! clic/id_stage: Add lower priv irq accept logic

* ariane_testharness: Unify CLIC and CLINT versions

* Makefile: Add missing rv_plic dependency for clic

* ariane_soc_pkg: Enable CLIC

* Revert "ci: Disable CLIC test"

This reverts commit 4195d3f.

* sram: Tie unused user signal to `0`

to avoid undriven user signals in the AXI interconnect

* id_stage: Ignore mie CSR when taking interrupts

mstatus.mie is checked via `global_enable` within the decoder

* ariane_tetsharness: Connect mtip and msip to CLIC

* cva6_config_pkg: Disable CVXIF

* ci: Use clic branch of riscv-tests

* clic: Change one-hot to ID irq

* clic: Aggregate core's CLIC logic in new module

* clic: Add kill handshake

* fixup! clic: Add kill handshake

* decoder: Remove unused block

* clic: Guard additions with param

* ariane_xilinx: Unify CLIC and CLINT modes

* clic: Remove mclicbase

According to the updated spec

* csr_regfile: Read 0, ignore writes from CLINT mode

* clic: Stilistic fixes

* csr_regfile: Add mtvt disclaimer

* ci: Point to pulp branch

* Revert "sram: Tie unused user signal to `0`"

This reverts commit add8320.
Will be merged separately

* ariane_pkg: Change struct param to pkg param

* clic: Bump

* Makefile: Update for clic

* ariane_testharness: Connect handshake kill logic

* ariane_xilinx: Connect handshake kill logic

* ariane_soc_pkg: Reduce clic interrupts to 64

* clic: Bump

* ariane_testharness: Fix zero fill size for irqs

* ariane_testharness/xilinx: Add unused cva6 ports

* clic: Update CI

* clic: Save/restore sil to/from scause

* ci: Align clic testcase naming

---------

Signed-off-by: Nils Wistoff <[email protected]>
Co-authored-by: aottaviano <[email protected]>
Co-authored-by: bluew <[email protected]>
Co-authored-by: Enrico Zelioli <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>

Bender.yml

@@ -37,10 +37,18 @@ sources:
         files:
           - core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
 
+      - target: cv64a6_imafdchsclic_sv39_hpdcache
+        files:
+          - core/include/cv64a6_imafdchsclic_sv39_hpdcache_config_pkg.sv
+
       - target: cv64a6_imafdc_sv39_wb
         files:
           - core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
 
+      - target: cv64a6_imafdchsclic_sv39_wb
+        files:
+          - core/include/cv64a6_imafdchsclic_sv39_hpdcache_config_pkg.sv
+
       - target: cv64a6_imafdch_sv39
         files:
           - core/include/cv64a6_imafdch_sv39_config_pkg.sv
@@ -70,8 +78,13 @@ sources:
         files:
           - core/cva6_accel_first_pass_decoder_stub.sv
 
+      # CLIC controller
+      - target: any(cv64a6_imafdchsclic_sv39_hpdcache, cv64a6_imafdchsclic_sv39_wb)
+        files:
+          - core/cva6_clic_controller.sv
+
       # MMU
-      - target: any(cv64a6_imafdcv_sv39, cv64a6_imafdc_sv39, cv64a6_imafdc_sv39_hpdcache, cv64a6_imafdc_sv39_wb, cv64a6_imafdch_sv39, cv64a6_imafdch_sv39_wb, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32)
+      - target: any(cv64a6_imafdcv_sv39, cv64a6_imafdc_sv39, cv64a6_imafdc_sv39_hpdcache, cv64a6_imafdchsclic_sv39_hpdcache, cv64a6_imafdc_sv39_wb, cv64a6_imafdchsclic_sv39_wb, cv64a6_imafdch_sv39, cv64a6_imafdch_sv39_wb, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32)
         files:
           - core/cva6_mmu/cva6_tlb.sv
           - core/cva6_mmu/cva6_shared_tlb.sv