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Riscv64 paging mraerino #25

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Riscv64 paging mraerino #25

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Commits on Sep 9, 2023

  1. initial boot page table 

    adapted from rCore see https://github.com/rcore-os/rCore

Signed-off-by: Stefan Hertenberger <[email protected]>
    @mraerino
    Stefan Hertenberger authored and mraerino committed Sep 9, 2023
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  2. riscv: remove unnecessary cast in virt devcons 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  3. riscv: reduce change in uart16550 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  4. riscv: print in platform init 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  5. riscv: linker script cleanup 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  6. riscv: DT/regblock/MMIO tests 

    NOTE: This is getting all `0000....` at this point.

Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  7. riscv: rework, add address mapping debug helper 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  8. riscv64: elaborate on SATP 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  9. WIP: riscv: try initializing UART natively 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  10. riscv: reduce UART MMIO debug prints 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  11. riscv: document PTE 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  12. riscv: factor out walk_dt, print binary sections 

    This aligns the riscv64 platform/virt kernel linker script with the aarch64 one.

Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  13. riscv: dump start of text region 

    This WORKS, i.e., prints what's in the binary, not just 0!

Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  14. riscv/memory: debug print address translation 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  15. riscv/platform/virt: fix up memory address offset 

    This causes hanging, but would be correct.
See also rCore `kernel/src/arch/riscv/consts.rs`.

Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  16. port/fdt: debug DT parsing 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  17. riscv: rework again, debug more... 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  18. I KNOW KUNG FU (kinda) 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  19. BACK TO NATIVE UART 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  20. awesome ASCII art 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  21. rework logo 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  22. riscv/platform/virt/devcons: remove unnecessary mut 

    Signed-off-by: Daniel Maslowski <[email protected]>
    @orangecms @mraerino
    orangecms authored and mraerino committed Sep 9, 2023
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  23. Implement page table reading and writing

    @mraerino
    mraerino committed Sep 9, 2023
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Commits on Sep 10, 2023

  1. Ensure cargo checks works for the workspace without flags 

    Signed-off-by: Marcus Weiner <[email protected]>
    @mraerino
    mraerino committed Sep 10, 2023
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  2. Move mem handling into module 

    Signed-off-by: Marcus Weiner <[email protected]>
    @mraerino
    mraerino committed Sep 10, 2023
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  3. Check page table bounds 

    Signed-off-by: Marcus Weiner <[email protected]>
    @mraerino
    mraerino committed Sep 10, 2023
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  4. Refactor to integer with access methods 

    Signed-off-by: Marcus Weiner <[email protected]>
    @mraerino
    mraerino committed Sep 10, 2023
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