Skip to content

Commit

Permalink
[mips] Add MXU instruction set.
Browse files Browse the repository at this point in the history
  • Loading branch information
@redstar
redstar committed Dec 26, 2020
1 parent e334c52 commit d898219
Show file tree
Hide file tree
Showing 14 changed files with 983 additions and 3 deletions.
137 changes: 136 additions & 1 deletion llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -204,6 +204,8 @@ class MipsAsmParser : public MCTargetAsmParser {
SMLoc S);
OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
OperandMatchResultTy parseImm(OperandVector &Operands);
OperandMatchResultTy parseOptn(OperandVector& Operands);
OperandMatchResultTy parseEptn(OperandVector& Operands);
OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
OperandMatchResultTy parseInvNum(OperandVector &Operands);
OperandMatchResultTy parseRegisterList(OperandVector &Operands);
Expand Down Expand Up @@ -430,6 +432,8 @@ class MipsAsmParser : public MCTargetAsmParser {

int matchMSA128CtrlRegisterName(StringRef Name);

int matchMXURegisterName(StringRef Name);

unsigned getReg(int RC, int RegNo);

/// Returns the internal register number for the current AT. Also checks if
Expand Down Expand Up @@ -694,6 +698,10 @@ class MipsAsmParser : public MCTargetAsmParser {
return (getSTI().getFeatureBits()[Mips::FeatureCnMipsP]);
}

bool hasMXU() const {
return (getSTI().getFeatureBits()[Mips::FeatureMXU]);
}

bool inPicMode() {
return IsPicEnabled;
}
Expand Down Expand Up @@ -811,10 +819,12 @@ class MipsOperand : public MCParsedAsmOperand {
RegKind_HWRegs = 256, /// HWRegs
RegKind_COP3 = 512, /// COP3
RegKind_COP0 = 1024, /// COP0
RegKind_MXU = 2048, /// MXU
/// Potentially any (e.g. $1)
RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
RegKind_CCR | RegKind_HWRegs | RegKind_COP3 | RegKind_COP0
RegKind_CCR | RegKind_HWRegs | RegKind_COP3 |
RegKind_COP0 | RegKind_MXU
};

private:
Expand Down Expand Up @@ -980,6 +990,15 @@ class MipsOperand : public MCParsedAsmOperand {
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to MXU and return the real register for the
/// current target.
unsigned getMXUReg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_MXU) && "Invalid access!");
// Use MXUSPlusCR class because it contains xr16.
unsigned ClassID = Mips::MXUSPlusCRRegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to COP0 and return the real register for the
/// current target.
unsigned getCOP0Reg() const {
Expand Down Expand Up @@ -1166,6 +1185,11 @@ class MipsOperand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createReg(getMSACtrlReg()));
}

void addMXUAsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(getMXUReg()));
}

void addCOP0AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(getCOP0Reg()));
Expand Down Expand Up @@ -1563,6 +1587,14 @@ class MipsOperand : public MCParsedAsmOperand {
return CreateReg(Index, Str, RegKind_MSACtrl, RegInfo, S, E, Parser);
}

/// Create a register that is definitely an MXU.
/// This is typically only used for named registers such as $xr1.
static std::unique_ptr<MipsOperand>
createMXUReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
SMLoc S, SMLoc E, MipsAsmParser &Parser) {
return CreateReg(Index, Str, RegKind_MXU, RegInfo, S, E, Parser);
}

static std::unique_ptr<MipsOperand>
CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
auto Op = std::make_unique<MipsOperand>(k_Immediate, Parser);
Expand Down Expand Up @@ -1691,6 +1723,10 @@ class MipsOperand : public MCParsedAsmOperand {
return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
}

bool isMXUAsmReg() const {
return isRegIdx() && RegIdx.Kind & RegKind_MXU && RegIdx.Index <= 16;
}

/// getStartLoc - Get the location of the first token of this operand.
SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Get the location of the last token of this operand.
Expand Down Expand Up @@ -6311,6 +6347,19 @@ int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
return CC;
}

int MipsAsmParser::matchMXURegisterName(StringRef Name) {
if (Name.startswith("xr")) {
StringRef NumString = Name.substr(2);
unsigned IntVal;
if (NumString.getAsInteger(10, IntVal))
return -1; // This is not an integer.
if (IntVal > 16) // There are only 16 MXU registers.
return -1;
return IntVal;
}
return -1;
}

bool MipsAsmParser::canUseATReg() {
return AssemblerOptions.back()->getATRegIndex() != 0;
}
Expand Down Expand Up @@ -6670,6 +6719,14 @@ MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
return MatchOperand_Success;
}

Index = matchMXURegisterName(Identifier);
if (Index != -1) {
Operands.push_back(MipsOperand::createMXUReg(
Index, Identifier, getContext().getRegisterInfo(), S,
getLexer().getLoc(), *this));
return MatchOperand_Success;
}

return MatchOperand_NoMatch;
}

Expand Down Expand Up @@ -6736,6 +6793,84 @@ MipsAsmParser::parseAnyRegister(OperandVector &Operands) {
return ResTy;
}

OperandMatchResultTy MipsAsmParser::parseOptn(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
LLVM_DEBUG(dbgs() << "parseOptn\n");

auto Token = Parser.getTok();

SMLoc S = Token.getLoc();

if (Token.is(AsmToken::Identifier)) {
LLVM_DEBUG(dbgs() << ".. identifier\n");
StringRef Identifier = Token.getIdentifier();
int64_t OpPat = StringSwitch<int>(Identifier)
.Case("ww", 0)
.Case("lw", 1)
.Case("hw", 2)
.Case("xw", 3)
.Default(-1);
if (OpPat != -1) {
Lex();
Operands.push_back(
MipsOperand::CreateImm(MCConstantExpr::create(OpPat, getContext()), S,
getLexer().getLoc(), *this));
return MatchOperand_Success;
}
} else if (Token.is(AsmToken::Integer)) {
LLVM_DEBUG(dbgs() << ".. integer\n");
int64_t OpPat = Token.getIntVal();
if (OpPat >= 0 && OpPat <= 3) {
Lex();
Operands.push_back(
MipsOperand::CreateImm(MCConstantExpr::create(OpPat, getContext()), S,
getLexer().getLoc(), *this));
return MatchOperand_Success;
}
}

return MatchOperand_NoMatch;
}

OperandMatchResultTy MipsAsmParser::parseEptn(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
LLVM_DEBUG(dbgs() << "parseEptn\n");

auto Token = Parser.getTok();

SMLoc S = Token.getLoc();

if (Token.is(AsmToken::Identifier)) {
LLVM_DEBUG(dbgs() << ".. identifier\n");
StringRef Identifier = Token.getIdentifier();
int64_t ExPat = StringSwitch<int>(Identifier)
.Case("aa", 0)
.Case("as", 1)
.Case("sa", 2)
.Case("ss", 3)
.Default(-1);
if (ExPat != -1) {
Lex();
Operands.push_back(
MipsOperand::CreateImm(MCConstantExpr::create(ExPat, getContext()), S,
getLexer().getLoc(), *this));
return MatchOperand_Success;
}
} else if (Token.is(AsmToken::Integer)) {
LLVM_DEBUG(dbgs() << ".. integer\n");
int64_t ExPat = Token.getIntVal();
if (ExPat >= 0 && ExPat <= 3) {
Lex();
Operands.push_back(
MipsOperand::CreateImm(MCConstantExpr::create(ExPat, getContext()), S,
getLexer().getLoc(), *this));
return MatchOperand_Success;
}
}

return MatchOperand_NoMatch;
}

OperandMatchResultTy
MipsAsmParser::parseJumpTarget(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
Expand Down
69 changes: 69 additions & 0 deletions llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -193,6 +193,22 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
uint64_t Address,
const void *Decoder);

static DecodeStatus DecodeMXUQRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);

static DecodeStatus DecodeMXUDRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);

static DecodeStatus DecodeMXUSRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);

static DecodeStatus DecodeMXUSPlusCRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);

static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
Expand Down Expand Up @@ -431,6 +447,9 @@ static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);

static DecodeStatus DecodeSimm12Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);

static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);

Expand Down Expand Up @@ -2183,6 +2202,50 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
return MCDisassembler::Success;
}

static DecodeStatus DecodeMXUQRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 15)
return MCDisassembler::Fail;

unsigned Reg = getReg(Decoder, Mips::MXUQRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}

static DecodeStatus DecodeMXUDRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 15)
return MCDisassembler::Fail;

unsigned Reg = getReg(Decoder, Mips::MXUDRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}

static DecodeStatus DecodeMXUSRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 15)
return MCDisassembler::Fail;

unsigned Reg = getReg(Decoder, Mips::MXUSRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}

static DecodeStatus DecodeMXUSPlusCRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 16)
return MCDisassembler::Fail;

unsigned Reg = getReg(Decoder, Mips::MXUSRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}

static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
Expand Down Expand Up @@ -2395,6 +2458,12 @@ static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
return MCDisassembler::Success;
}

static DecodeStatus DecodeSimm12Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Insn) * 4));
return MCDisassembler::Success;
}

static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
int32_t DecodedValue;
Expand Down
10 changes: 10 additions & 0 deletions llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -998,6 +998,16 @@ MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
return 0;
}

unsigned
MipsMCCodeEmitter::getSimm12Lsl2Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
assert(MI.getOperand(OpNo).isImm());
unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
assert((Res & 3) == 0);
return Res >> 2;
}

unsigned
MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -237,6 +237,10 @@ class MipsMCCodeEmitter : public MCCodeEmitter {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

unsigned getSimm12Lsl2Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/Mips/Mips.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -186,6 +186,9 @@ def FeatureCnMipsP : SubtargetFeature<"cnmipsp", "HasCnMipsP",
"true", "Octeon+ cnMIPS Support",
[FeatureCnMips]>;

def FeatureMXU : SubtargetFeature<"mxu", "HasMXU",
"true", "Ingenic MXU Support">;

def FeatureUseTCCInDIV : SubtargetFeature<
"use-tcc-in-div",
"UseTCCInDIV", "false",
Expand Down
10 changes: 10 additions & 0 deletions llvm/lib/Target/Mips/MipsInstrInfo.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -215,6 +215,8 @@ def HasCnMipsP : Predicate<"Subtarget->hasCnMipsP()">,
AssemblerPredicate<(all_of FeatureCnMipsP)>;
def NotCnMipsP : Predicate<"!Subtarget->hasCnMipsP()">,
AssemblerPredicate<(all_of (not FeatureCnMipsP))>;
def HasMXU : Predicate<"Subtarget->hasMXU()">,
AssemblerPredicate<(all_of FeatureMXU)>;
def IsSym32 : Predicate<"Subtarget->hasSym32()">,
AssemblerPredicate<(all_of FeatureSym32)>;
def IsSym64 : Predicate<"!Subtarget->hasSym32()">,
Expand Down Expand Up @@ -455,6 +457,10 @@ class ASE_MIPS64_CNMIPS {
list<Predicate> ASEPredicate = [HasMips64, HasCnMips];
}

class ASE_MXU {
list<Predicate> ASEPredicate = [HasMXU];
}

class ASE_MSA {
list<Predicate> ASEPredicate = [HasMSA];
}
Expand Down Expand Up @@ -3386,6 +3392,10 @@ include "MipsDSPInstrInfo.td"
include "MipsMSAInstrFormats.td"
include "MipsMSAInstrInfo.td"

// MXU
include "MipsMXUInstrFormats.td"
include "MipsMXUInstrInfo.td"

// EVA
include "MipsEVAInstrFormats.td"
include "MipsEVAInstrInfo.td"
Expand Down
Loading

0 comments on commit d898219

Please sign in to comment.