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/*==========================================================================*/ | ||
/* Sail */ | ||
/* */ | ||
/* Sail and the Sail architecture models here, comprising all files and */ | ||
/* directories except the ASL-derived Sail code in the aarch64 directory, */ | ||
/* are subject to the BSD two-clause licence below. */ | ||
/* */ | ||
/* The ASL derived parts of the ARMv8.3 specification in */ | ||
/* aarch64/no_vector and aarch64/full are copyright ARM Ltd. */ | ||
/* */ | ||
/* Copyright (c) 2013-2021 */ | ||
/* Kathyrn Gray */ | ||
/* Shaked Flur */ | ||
/* Stephen Kell */ | ||
/* Gabriel Kerneis */ | ||
/* Robert Norton-Wright */ | ||
/* Christopher Pulte */ | ||
/* Peter Sewell */ | ||
/* Alasdair Armstrong */ | ||
/* Brian Campbell */ | ||
/* Thomas Bauereiss */ | ||
/* Anthony Fox */ | ||
/* Jon French */ | ||
/* Dominic Mulligan */ | ||
/* Stephen Kell */ | ||
/* Mark Wassell */ | ||
/* Alastair Reid (Arm Ltd) */ | ||
/* */ | ||
/* All rights reserved. */ | ||
/* */ | ||
/* This work was partially supported by EPSRC grant EP/K008528/1 <a */ | ||
/* href="http://www.cl.cam.ac.uk/users/pes20/rems">REMS: Rigorous */ | ||
/* Engineering for Mainstream Systems</a>, an ARM iCASE award, EPSRC IAA */ | ||
/* KTF funding, and donations from Arm. This project has received */ | ||
/* funding from the European Research Council (ERC) under the European */ | ||
/* Union’s Horizon 2020 research and innovation programme (grant */ | ||
/* agreement No 789108, ELVER). */ | ||
/* */ | ||
/* This software was developed by SRI International and the University of */ | ||
/* Cambridge Computer Laboratory (Department of Computer Science and */ | ||
/* Technology) under DARPA/AFRL contracts FA8650-18-C-7809 ("CIFV") */ | ||
/* and FA8750-10-C-0237 ("CTSRD"). */ | ||
/* */ | ||
/* SPDX-License-Identifier: BSD-2-Clause */ | ||
/*==========================================================================*/ | ||
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$ifndef _DEC_BITS | ||
$define _DEC_BITS | ||
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$include <option.sail> | ||
$include <vector.sail> | ||
$include <string.sail> | ||
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val "parse_dec_bits" : forall 'n, 'n > 0. (int('n), string) -> bits('n) | ||
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val "valid_dec_bits" : forall 'n, 'n > 0. (int('n), string) -> bool | ||
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val dec_bits : forall 'n, 'n > 0. bits('n) <-> (int('n), string) | ||
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function dec_bits_forwards(bv) = (length(bv), dec_str(unsigned(bv))) | ||
function dec_bits_forwards_matches(bv) = true | ||
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function dec_bits_backwards(n, str) = parse_dec_bits(n, str) | ||
function dec_bits_backwards_matches(n, str) = valid_dec_bits(n, str) | ||
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mapping dec_bits_1 : bits(1) <-> string = { dec_bits(1, s) <-> s } | ||
mapping dec_bits_8 : bits(8) <-> string = { dec_bits(8, s) <-> s } | ||
mapping dec_bits_32 : bits(32) <-> string = { dec_bits(32, s) <-> s } | ||
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$endif _DEC_BITS |
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ok | ||
ok | ||
ok | ||
ok | ||
ok | ||
ok |
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default Order dec | ||
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$include <prelude.sail> | ||
$include <dec_bits.sail> | ||
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function main() -> unit = { | ||
match dec_bits_1("1") { | ||
0b1 => print_endline("ok"), | ||
_ => print_endline("fail"), | ||
}; | ||
match dec_bits_1(0b1) { | ||
"1" => print_endline("ok"), | ||
_ => print_endline("fail"), | ||
}; | ||
match dec_bits_8("255") { | ||
0b1111_1111 => print_endline("ok"), | ||
_ => print_endline("fail"), | ||
}; | ||
match dec_bits_8(0b1111_1111) { | ||
"255" => print_endline("ok"), | ||
s => print_endline(s), | ||
}; | ||
match dec_bits_8(0b1101_0000) { | ||
"208" => print_endline("ok"), | ||
s => print_endline("fail"), | ||
}; | ||
match dec_bits_8("208") { | ||
0b1101_0000 => print_endline("ok"), | ||
s => print_endline("fail"), | ||
}; | ||
} |