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This is a central place for me to keep some VHDL, and Verilog code that is often repeated in different projects.

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
README.md		README.md
common_functions.vhd		common_functions.vhd
generic_counter.vhd		generic_counter.vhd
generic_pipeline.vhd		generic_pipeline.vhd
generic_register.vhd		generic_register.vhd
generic_register_chain.vhd		generic_register_chain.vhd

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