Merge pull request #416 from davidharrishmc/master

Renamed rv32e_unratified to rv32e_m because E extension was ratified …

CHANGELOG.md

@@ -1,4 +1,9 @@
 # CHANGELOG
+
+## [3.8.5] -- 2013-12-23
+- Renamed rv32e_unratified to rv32e_m because the E extension has been ratified January 2023
+- Copied missing ebreak.S and ecall.S tests from rv32i_m/privilege to rv32e_m/privilege and update ISA for E
+
 ## [3.8.3] - 2023-11-30
 - Add Zicond ISA extension support
 

riscv-test-suite/rv32e_m/privilege/src/ebreak.S

@@ -0,0 +1,76 @@
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the ebreak instruction of the RISC-V I extension.
+// 
+
+#include "model_test.h"
+#include "arch_test.h"
+
+RVTEST_ISA("RV32E_Zicsr")
+
+# Test code region
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+
+#ifdef TEST_CASE_1
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*E.*Zicsr.*); def rvtest_mtrap_routine=True; def RVTEST_E = True; def TEST_CASE_1=True",ebreak)
+    # ---------------------------------------------------------------------------------------------
+
+    LA(     x1,test_A_res)
+
+    LI(     x2,0x11111111)
+    .option push;
+    .option norvc;
+    ebreak
+    nop
+    nop
+    sw      x0, 0(x1)
+    sw      x2, 4(x1)
+    .option pop;
+
+    RVMODEL_IO_WRITE_STR(x14, "# Test part A - test EBREAK\n");
+
+    RVMODEL_IO_WRITE_STR(x14, "# Test End\n")
+
+#endif
+
+ # ---------------------------------------------------------------------------------------------
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+# Input data section.
+    .data
+    .align 4
+RVTEST_DATA_END
+
+# Output data section.
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+test_A_res:
+  .fill 2, 4, 0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+mtrap_sigptr:
+  .fill 4, 4, 0xdeadbeef
+#endif
+
+#ifdef rvtest_gpr_save
+gpr_save:
+  .fill 32*(XLEN/32), 4, 0xdeadbeef
+#endif
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END

riscv-test-suite/rv32e_m/privilege/src/ecall.S

@@ -0,0 +1,72 @@
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the ecall instruction of the RISC-V I extension.
+// 
+
+#include "model_test.h"
+#include "arch_test.h"
+
+RVTEST_ISA("RV32E_Zicsr")
+
+# Test code region
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*E.*Zicsr.*); def rvtest_mtrap_routine=True; def RVTEST_E = True; def TEST_CASE_1=True",ecall)
+
+    # ---------------------------------------------------------------------------------------------
+    LA(     x1,test_A_res)
+
+    LI(     x2,0x11111111)
+    ecall
+    nop
+    nop
+    sw      x0, 0(x1)
+    sw      x2, 4(x1)
+
+    RVMODEL_IO_WRITE_STR(x14, "# Test part A - test ECALL\n");
+
+    RVMODEL_IO_WRITE_STR(x14, "# Test End\n")
+
+#endif
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+# Input data section.
+    .data
+    .align 4
+RVTEST_DATA_END
+
+# Output data section.
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+
+test_A_res:
+    .fill 2, 4, 0xdeadbeef
+
+mtrap_sigptr:
+  .fill 4, 4, 0xdeadbeef
+
+#ifdef rvtest_gpr_save
+gpr_save:
+  .fill 32*(XLEN/32), 4, 0xdeadbeef
+#endif
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END