Merge pull request #357 from ahadali-10x/atomic_ACTs

Add tests for Atomic Memory Operation(AMO) instructions
riscv-non-isa · Sep 27, 2023 · f66d8ff · f66d8ff
2 parents 46cf99d + c4a7733
commit f66d8ff
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,5 +1,9 @@
 # CHANGELOG
 
+## [3.7.1] - 2023-08-03
+- Add ACTs for Atomic Extension excluding Lr/Sc Instructions.
+- Added Test macro for the execution of atomic instructions.
+
 ## [3.7.0] - 2023-05-16
 - Updated the LI macro
 - Make Trap handler compatible for RV32E

diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h
@@ -472,6 +472,18 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg)
     RVTEST_SIGUPD_FID(swreg,destreg,flagreg)	;\
     RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
 
+//Tests for atomic memory operation(AMO) instructions
+#define TEST_AMO_OP(inst, destreg, origptr, reg2, origval, updval, sigptr, ...) ;\
+      .if NARG(__VA_ARGS__) == 1			;\
+	.set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))	;\
+      .endif						;\
+      LI(reg2, MASK_XLEN(origval))			;\
+      RVTEST_SIGUPD(sigptr, reg2) /*Write original AMO src */ ;\
+      LI(reg2, MASK_XLEN(updval)) ;\
+      addi origptr, sigptr, offset-REGWIDTH /* Calculate where orig AMO src is stored */ ;\
+      inst destreg, reg2, (origptr) /*origval -> destreg; updated val -> (origptr) */ ;\
+      RVTEST_SIGUPD(sigptr, destreg) /* write original AMO val */
+
 #define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg)	;\
     TEST_CASE(testreg, destreg, correctval, swreg, offset, \
       LA testreg, 1f			;\