Add arch-tests for Smcsrind and Sscsrind - Draft #380
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Description
Add arch-tests for Smcsrind and Sscsrind fast-track extension
Note that these two indirect CSR extensions define a means to access
an array of registers via CSRs which will be defined by other extensions.
Until those other extensions are defined, the data read back is undefined.
So these arch tests primarily test the existence of the Smcsrind/Sscsrind
CSRs and access exceptions.
Related Issues
SAIL does not currently support Smcsrind, Sscsrind, Smstateen, Hypervisor mode.
Smcsrind/Sscsrind supported in spike: riscv-software-src/riscv-isa-sim@60c08b1
Sscsrind interaction with Smstateen still needs to be added to spike.
Ratified/Unratified Extensions
[x] Ratified
[ ] Unratified
List Extensions
These extensions are described in the PDF spec available at:
https://github.com/riscv/riscv-smcntrpmf/releases/download/v1.0_rc4-frozen/riscv-smcntrpmf-v1.0_rc4.pdf
Reference Model Used
Mandatory Checklist:
All tests are compliant with the test-format spec present in this repo ?
Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
Ran the new tests on RISCOF in [coverage mode](https://riscof.readthedocs.io/en/stable/commands.html#coverage
I will need help running coverage and other riscof infrastructure using spike only. SAIL is probably a long time from being able to support smstateen/hypervisor which is required by Sscsrind extension. I also had problems getting a log from spike and making sure spike Smcsrind extension is enabled by the tests.
Link to Google-Drive folder containing the new coverage reports (See this for more info): < SPECIFY HERE >
Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE >
Changelog entry created with a minor patch
Optional Checklist: