Virtual Memory SV-32 Address Translation Scheme Tests and Covergroups

[MuhammadHammad001]

Description

This PR contains the tests and covergroups for Virtual Memory SV32 address translation scheme. The tests and covergroups are written using the following Test Plan

Related Issues

This PR has a dependency on the PR#

Ratified/Unratified Extensions

• Ratified
• Unratified

List Extensions

NA

Reference Model Used

• SAIL
• Spike
• Other - < SPECIFY HERE >

Mandatory Checklist:

• All tests are compliant with the test-format spec present in this repo ?
• Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
• Ran the new tests on RISCOF in coverage mode
• Link to Google-Drive folder containing the new coverage reports available here
• Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE >
• Changelog entry created with a minor patch

Optional Checklist:

• RISCV-V CTG PR link if tests were generated using it : < SPECIFY HERE >
• Were the tests hand-written/modified ?
• Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
• If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

[UmerShahidengr]

@allenjbaum CI is passing for these tests too, please review these tests.

[MuhammadHammad001]

@allenjbaum @UmerShahidengr Covergroups have been updated and now are written using the translator format.