Releases: riscv-non-isa/riscv-arch-test
Releases · riscv-non-isa/riscv-arch-test
3.7.1
- Add ACTs for Atomic Extension excluding Lr/Sc Instructions.
- Added Test macro for the execution of atomic instructions.
3.7.0
- Updated the LI macro
- Make Trap handler compatible for RV32E
- Remove the warning messages issue #336
- Added Macros for testing Virtual Memory in Sv32 mode.
3.6.8
- Fix broken hyperlink in README
3.6.7
3.6.6
- Removed stale zext.h-01.S test case superseded by zext.h_64-01.S
3.6.5
- Fix test condition in RVTEST_CASE for
c.ebreak
(RV32 and RV64) test.
3.6.4
- In Zifencei test, updated the ISA string
zifencei
formarch
flag of toolchain. - Set the default definition of
RVMODEL_FENCEI
tonop
in trap-handler.
3.6.3
- Split LI() macro for RV32 and RV64 to eliminate warning messages.
- Reduce the use of LA() macro by declaring fixed size offsets in save area.
- Updated RVTEST_GOTO_MMODE macro
- Updated _MODE_()trap_sig_sv, replaced an LA(rvtest_trap_sig) by calculating initial_Xtrap_sigptr + (Mtrap_sigptr-initial_Mtrap-sigptr)
- Similar changes are made in chk__MODE_()trapsig_overrun macro.
- Updated RVTEST_TRAP_SAVEAREA. Also added vmem segment in the save area.
- Added infrastructure support traps from S/U mode with Virtualization enabled
3.6.2
- Remove RV64IB from ISA list of zext test.
3.6.1
- Fix satp restore condition.