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Releases: riscv-non-isa/riscv-arch-test

3.7.1

27 Sep 04:54
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  • Add ACTs for Atomic Extension excluding Lr/Sc Instructions.
  • Added Test macro for the execution of atomic instructions.

3.7.0

14 Jul 12:55
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  • Updated the LI macro
  • Make Trap handler compatible for RV32E
  • Remove the warning messages issue #336
  • Added Macros for testing Virtual Memory in Sv32 mode.

3.6.8

22 Jun 15:45
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  • Fix broken hyperlink in README

3.6.7

22 Jun 15:38
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  • Specify new optional model macro RVMODEL_MTVEC_ALIGN to define new macro MTVEC_ALIGN in arch_test.h for issue #351

3.6.6

22 Jun 15:24
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  • Removed stale zext.h-01.S test case superseded by zext.h_64-01.S

3.6.5

08 May 05:08
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  • Fix test condition in RVTEST_CASE for c.ebreak (RV32 and RV64) test.

3.6.4

06 May 02:22
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  • In Zifencei test, updated the ISA string zifencei for march flag of toolchain.
  • Set the default definition of RVMODEL_FENCEI to nop in trap-handler.

3.6.3

19 Apr 08:20
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  • Split LI() macro for RV32 and RV64 to eliminate warning messages.
  • Reduce the use of LA() macro by declaring fixed size offsets in save area.
  • Updated RVTEST_GOTO_MMODE macro
  • Updated _MODE_()trap_sig_sv, replaced an LA(rvtest_trap_sig) by calculating initial_Xtrap_sigptr + (Mtrap_sigptr-initial_Mtrap-sigptr)
  • Similar changes are made in chk__MODE_()trapsig_overrun macro.
  • Updated RVTEST_TRAP_SAVEAREA. Also added vmem segment in the save area.
  • Added infrastructure support traps from S/U mode with Virtualization enabled

3.6.2

08 Feb 14:13
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  • Remove RV64IB from ISA list of zext test.

3.6.1

30 Jan 06:33
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  • Fix satp restore condition.