Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fix hard-coded section references #1804

Merged
merged 6 commits into from
Jan 16, 2025
Merged

Fix hard-coded section references #1804

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
07e3bd4
Fix hardcoded section numbers in C chapter
aswaterman Jan 15, 2025
ab75270
Fix hardcoded section numbers in intro
aswaterman Jan 15, 2025
772a1c9
Remove unneeded hardcoded section references in scalar crypto
aswaterman Jan 15, 2025
930a42c
Fix hardcoded section references in pointer masking
aswaterman Jan 15, 2025
a16b226
Fix hardcoded section references in scalar crypto
aswaterman Jan 15, 2025
0b155c9
Fix hardcoded section references in memory model appendix
aswaterman Jan 15, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion src/c-st-ext.adoc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -909,7 +909,7 @@ valid for certain operands; when invalid, they are marked either _RES_
to indicate that the opcode is reserved for future standard extensions;
_Custom_ to indicate that the opcode is designated for custom
extensions; or _HINT_ to indicate that the opcode is reserved for
microarchitectural hints (see <<rvc-hints, Section 18.7>>).
microarchitectural hints (see <<rvc-hints>>).

<<<

Expand Down
2 changes: 1 addition & 1 deletion src/intro.adoc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -172,7 +172,7 @@ responsibility ends if the hart is terminated. The following events
constitute forward progress:

* The retirement of an instruction.
* A trap, as defined in <<trap-defn, Section 1.6>>.
* A trap, as defined in <<trap-defn>>.
* Any other event defined by an extension to constitute forward
progress.

Expand Down
9 changes: 4 additions & 5 deletions src/mm-formal.adoc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,11 +8,10 @@ discrepancies are unintended; the expectation is that the models
describe exactly the same sets of legal behaviors.

This appendix should be treated as commentary; all normative material is
provided in <<memorymodel, Chapter 17>> and in the rest of
the main body of the ISA specification. All currently known
discrepancies are listed in
<<discrepancies, Section A.7>>. Any other
discrepancies are unintentional.
provided in <<memorymodel>> and in the rest of
the main body of the ISA specification.
All currently known discrepancies are listed in <<discrepancies>>.
Any other discrepancies are unintentional.

[[alloy]]
=== Formal Axiomatic Specification in Alloy
Expand Down
79 changes: 27 additions & 52 deletions src/scalar-crypto.adoc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2017,7 +2017,7 @@ Included in::

Synopsis::
Implements the Sigma0 transformation function as used in
the SHA2-256 hash function cite:[nist:fips:180:4] (Section 4.1.2).
the SHA2-256 hash function cite:[nist:fips:180:4].

Mnemonic::
sha256sig0 rd, rs1
Expand Down Expand Up @@ -2083,7 +2083,7 @@ Included in::

Synopsis::
Implements the Sigma1 transformation function as used in
the SHA2-256 hash function cite:[nist:fips:180:4] (Section 4.1.2).
the SHA2-256 hash function cite:[nist:fips:180:4].

Mnemonic::
sha256sig1 rd, rs1
Expand Down Expand Up @@ -2149,7 +2149,7 @@ Included in::

Synopsis::
Implements the Sum0 transformation function as used in
the SHA2-256 hash function cite:[nist:fips:180:4] (Section 4.1.2).
the SHA2-256 hash function cite:[nist:fips:180:4].

Mnemonic::
sha256sum0 rd, rs1
Expand Down Expand Up @@ -2215,7 +2215,7 @@ Included in::

Synopsis::
Implements the Sum1 transformation function as used in
the SHA2-256 hash function cite:[nist:fips:180:4] (Section 4.1.2).
the SHA2-256 hash function cite:[nist:fips:180:4].

Mnemonic::
sha256sum1 rd, rs1
Expand Down Expand Up @@ -2281,7 +2281,7 @@ Included in::

Synopsis::
Implements the _high half_ of the Sigma0 transformation, as
used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3).
used in the SHA2-512 hash function cite:[nist:fips:180:4].

Mnemonic::
sha512sig0h rd, rs1, rs2
Expand Down Expand Up @@ -2355,7 +2355,7 @@ Included in::

Synopsis::
Implements the _low half_ of the Sigma0 transformation, as
used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3).
used in the SHA2-512 hash function cite:[nist:fips:180:4].

Mnemonic::
sha512sig0l rd, rs1, rs2
Expand Down Expand Up @@ -2429,7 +2429,7 @@ Included in::

Synopsis::
Implements the _high half_ of the Sigma1 transformation, as
used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3).
used in the SHA2-512 hash function cite:[nist:fips:180:4].

Mnemonic::
sha512sig1h rd, rs1, rs2
Expand Down Expand Up @@ -2503,7 +2503,7 @@ Included in::

Synopsis::
Implements the _low half_ of the Sigma1 transformation, as
used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3).
used in the SHA2-512 hash function cite:[nist:fips:180:4].

Mnemonic::
sha512sig1l rd, rs1, rs2
Expand Down Expand Up @@ -2577,7 +2577,7 @@ Included in::

Synopsis::
Implements the Sum0 transformation, as
used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3).
used in the SHA2-512 hash function cite:[nist:fips:180:4].

Mnemonic::
sha512sum0r rd, rs1, rs2
Expand Down Expand Up @@ -2651,7 +2651,7 @@ Included in::

Synopsis::
Implements the Sum1 transformation, as
used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3).
used in the SHA2-512 hash function cite:[nist:fips:180:4].

Mnemonic::
sha512sum1r rd, rs1, rs2
Expand Down Expand Up @@ -2725,7 +2725,7 @@ Included in::

Synopsis::
Implements the Sigma0 transformation function as used in
the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3).
the SHA2-512 hash function cite:[nist:fips:180:4].

Mnemonic::
sha512sig0 rd, rs1
Expand Down Expand Up @@ -2785,7 +2785,7 @@ Included in::

Synopsis::
Implements the Sigma1 transformation function as used in
the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3).
the SHA2-512 hash function cite:[nist:fips:180:4].

Mnemonic::
sha512sig1 rd, rs1
Expand Down Expand Up @@ -2845,7 +2845,7 @@ Included in::

Synopsis::
Implements the Sum0 transformation function as used in
the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3).
the SHA2-512 hash function cite:[nist:fips:180:4].

Mnemonic::
sha512sum0 rd, rs1
Expand Down Expand Up @@ -2905,7 +2905,7 @@ Included in::

Synopsis::
Implements the Sum1 transformation function as used in
the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3).
the SHA2-512 hash function cite:[nist:fips:180:4].

Mnemonic::
sha512sum1 rd, rs1
Expand Down Expand Up @@ -4237,7 +4237,7 @@ contributed to the RISC-V cryptography extension.

Many of the primitive operations used in symmetric key cryptography
and cryptographic hash functions are well supported by the
RISC-V Bitmanip cite:[riscv:bitmanip:repo] extensions.
RISC-V Bitmanip extensions (see <<bits>>).

NOTE: This section repeats much of the information in
<<zbkb-sc>>,
Expand Down Expand Up @@ -4267,8 +4267,7 @@ RV32, RV64: RV64 only:
rori rd, rs1, imm roriw rd, rs1, imm
----

See cite:[riscv:bitmanip:draft] (Section 3.1.1) for details of
these instructions.
See <<zbkb>> for details of these instructions.

.Notes to software developers
[NOTE,caption="SH"]
Expand All @@ -4286,24 +4285,12 @@ class of block ciphers and stream ciphers.
===== Bit & Byte Permutations

----
RV32:
brev8 rd, rs1 // grevi rd, rs1, 7 - Reverse bits in bytes
rev8 rd, rs1 // grevi rd, rs1, 24 - Reverse bytes in 32-bit word

RV64:
brev8 rd, rs1 // grevi rd, rs1, 7 - Reverse bits in bytes
rev8 rd, rs1 // grevi rd, rs1, 56 - Reverse bytes in 64-bit word
RV32, RV64:
brev8 rd, rs1
rev8 rd, rs1
----

The scalar cryptography extension provides the following instructions for
manipulating the bit and byte endianness of data.
They are all parameterisations of the Generalised Reverse with Immediate
(`grevi` instruction.
The scalar cryptography extension requires _only_ the above instances
of `grevi` be implemented, which can be invoked via their pseudoinstructions.

The full specification of the `grevi` instruction is available in
cite:[riscv:bitmanip:draft] (Section 2.2.2).
See <<zbkb>> for details of these instructions.

.Notes to software developers
[NOTE,caption="SH"]
Expand All @@ -4316,19 +4303,11 @@ of Galois/Counter Mode (GCM) cite:[nist:gcm].

----
RV32:
zip rd, rs1 // shfli rd, rs1, 15 - Bit interleave
unzip rd, rs1 // unshfli rd, rs1, 15 - Bit de-interleave
zip rd, rs1
unzip rd, rs1
----

The `zip` and `unzip` pseudoinstructions are specific instances of
the more general `shfli` and `unshfli` instructions.
The scalar cryptography extension requires _only_ the above instances
of `[un]shfli` be implemented, which can be invoked via their
pseudoinstructions.
Only RV32 implementations require these instructions.

The full specification of the `shfli` instruction is available in
cite:[riscv:bitmanip:draft] (Section 2.2.3).
See <<zbkb>> for details of these instructions.

.Notes to software developers
[NOTE,caption="SH"]
Expand All @@ -4349,8 +4328,7 @@ RV32, RV64:
clmulh rd, rs1, rs2
----

See cite:[riscv:bitmanip:draft] (Section 2.6) for details of
this instruction.
See <<zbkc>> for details of these instructions.
See <<crypto_scalar_zkt>> for additional implementation
requirements for these instructions, related to data independent
execution latency.
Expand All @@ -4374,8 +4352,7 @@ RV32, RV64:
xnor rd, rs1, rs2
----

See cite:[riscv:bitmanip:draft] (Section 2.1.3) for details of
these instructions.
See <<zbkb>> for details of these instructions.
These instructions are useful inside hash functions, block ciphers and
for implementing software based side-channel countermeasures like masking.
The `andn` instruction is also useful for constant time word-select
Expand All @@ -4398,8 +4375,7 @@ RV32, RV64: RV64:
packh rd, rs1, rs2
----

See cite:[riscv:bitmanip:draft] (Section 2.1.4) for details of
these instructions.
See <<zbkb>> for details of these instructions.

.Notes to software developers
[NOTE,caption="SH"]
Expand All @@ -4422,8 +4398,7 @@ RV32, RV64:
xperm8 rd, rs1, rs2
----

See cite:[riscv:bitmanip:draft] (Section 2.2.4) for a complete
description of this instruction.
See <<zbkx>> for a complete description of these instructions.

The `xperm4` instruction operates on nibbles.
`GPR[rs1]` contains a vector of `XLEN/4` 4-bit elements.
Expand Down
3 changes: 2 additions & 1 deletion src/zpm.adoc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ While we describe the high-level concepts of pointer masking as if it was a sing

==== Definitions

We now define basic terms. Note that these rely on the definition of an “ignore” transformation, which is defined in Chapter 2.2.
We now define basic terms. Note that these rely on the definition of an “ignore” transformation, which is defined in <<sec-ignore-transform>>.

* **Effective address (as defined in the RISC-V Base ISA):** A load/store effective address sent to the memory subsystem (e.g., as generated during the execution of load/store instructions). This does not include addresses corresponding to implicit accesses, such as page table walks.

Expand All @@ -33,6 +33,7 @@ We now define basic terms. Note that these rely on the definition of an “ignor

* **VBITS:** The bits within a virtual address that affect which memory is addressed. These are the bits of an address which are used to index into page tables.

[[sec-ignore-transform]]
==== The “Ignore” Transformation

The ignore transformation differs depending on whether it applies to a virtual or physical address. For virtual addresses, it replaces the upper PMLEN bits with the sign extension of the PMLEN+1st bit.
Expand Down
Loading