Merge pull request #8 from ASaltFishy/main

Refine the spec according to Qualcomm's comments
riscv · Oct 14, 2023 · 66070a8 · 66070a8
2 parents dc37fda + 5f9afc2
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diff --git a/images/RV32_SPMP_address_register_format.png b/images/RV32_SPMP_address_register_format.png
diff --git a/images/RV32_SPMP_address_register_format.svg b/images/RV32_SPMP_address_register_format.svg
diff --git a/images/RV64_SPMP_address_register_format.png b/images/RV64_SPMP_address_register_format.png
diff --git a/images/RV64_SPMP_address_register_format.svg b/images/RV64_SPMP_address_register_format.svg
diff --git a/images/SPMP_configuration_register_format.png b/images/SPMP_configuration_register_format.png
diff --git a/images/SPMP_configuration_register_format.svg b/images/SPMP_configuration_register_format.svg
diff --git a/images/SPMP_domain_switch_register_format.svg b/images/SPMP_domain_switch_register_format.svg
diff --git a/intro.adoc b/intro.adoc
@@ -1,7 +1,7 @@
 [[intro]]
 == Introduction
 
-This document describes RISC-V S-mode Physical Memory Protection (SPMP) proposal to provide isolation when MMU is unavailable.
+This document describes RISC-V S-mode Physical Memory Protection (SPMP) proposal to provide isolation when MMU is unavailable or disabled.
 RISC-V based processors recently stimulated great interest in the emerging internet of things (IoT). However, as page-based virtual memory (MMU) is usually unavailable on IoT devices, it is hard to isolate the S-mode OSes (e.g., RTOS) and user-mode applications.
 To support secure processing and isolate faults of U-mode software, the SPMP is desirable to enable S-mode OS to limit the physical addresses accessible by U-mode software on a hart.
 
diff --git a/rv-spmp-spec.pdf b/rv-spmp-spec.pdf