Fixing typos and avoiding implication that ordering bits were optional.

chapter2.adoc

@@ -46,7 +46,8 @@ Description::
 
 This instruction loads 2^width^ bytes of memory from rs1 atomically.
 If the size (2^width+3^) is less than XLEN, it is sign-extended to fill the destination register.
-This load must have the ordering annotation _aq_, and may have ordering annotation _rl_ encoded in the instruction: if the bit _aq_ is set, the instruction has an "acquire-RCsc" annotation, and if the bit _rl_ is set, the instruction has a "release-RCsc" annotation.
+This load must have the ordering annotation _aq_ and may have ordering annotation _rl_ encoded in the instruction.
+The instruction always has an "acquire-RCsc" annotation, and if the bit _rl_ is set the instruction has a "release-RCsc" annotation.
 +
 The versions without the _aq_ bit set are RESERVED.
 LD.{AQ, AQRL} is RV64-only.
@@ -96,7 +97,8 @@ Encoding::
 Description::
 
 This instruction stores 2^width^ bytes of memory from rs1 atomically.
-This store must have ordering annotation _rl_, and may have ordering annotation _aq_ encoded in the instruction: if the bit _aq_ is set, the instruction has an "acquire-RCsc" annotation, and if the bit _rl_ is set, the instruction has a "release-RCsc" annotation.
+This store must have ordering annotation _rl_ and may have ordering annotation _aq_ encoded in the instruction.
+The instruction always has an "release-RCsc" annotation, and if the bit _aq_ is set the instruction has a "acquire-RCsc" annotation.
 +
 The versions without the _rl_ bit set are RESERVED.
 SD.{RL, AQRL} is RV64-only.