Adding sections on non-idempotent memory and fault handling

- Consistent with Zcmp behavior
- Based on Allen Baum's feedback

zilsd.adoc

@@ -36,4 +36,23 @@ These instructions are mutually exclusive with Zcf.
 
 LD and C.LD instructions with destination `x0` are processed as any other load, but the result is discarded entirely. Specifically, a load pair to `x0` does not cause `x1` to be written. For C.LDSP, usage of `x0` as the destination is reserved.
 
-When using `x0` as `src` of SD, C.SD, or C.SDSP, the entire 64-bit operand is zero — i.e., register `x1` is not accessed.
+When using `x0` as `src` of SD, C.SD, or C.SDSP, the entire 64-bit operand is zero — i.e., register `x1` is not accessed.
+
+=== Fault Handling
+
+In implementations that crack Zilsd instructions for sequential execution, correct execution requires addressing idempotent memory, because the core must be able to handle traps detected during the sequence. The entire sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence.
+
+If a trap occurs during the sequence then xEPC is updated with the PC of the instruction, xTVAL (if not read-only-zero) updated with the bad address if it was an access fault and xCAUSE updated with the type of trap.
+
+[NOTE]
+====
+It is implementation defined whether interrupts can also be taken during the sequence execution.
+====
+
+=== Non-idempotent memory handling
+
+An implementation may have a requirement to issue a load/store pair instruction to non-idempotent memory.
+
+If the core implementation does not support Zilsd instructions to non-idempotent memories (e.g. if atomicity cannot be guaranteed), the core may use an idempotency PMA to detect it and take a load or store access fault exception in order to avoid unpredictable results.
+
+Software should only use these instructions on non-idempotent memory regions when software can tolerate the required memory accesses being issued repeatedly in the case that they cause exceptions.