Adding a note to clarify natural alignment of the instructions #17
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tovine
reviewed
May 28, 2024
| @@ -14,6 +14,11 @@ The Zilsd extension adds the following RV32-only instructions: | |||
| - LD loads a 64-bit value into registers `rd` and `rd+1` | |||
| - SD stores a 64-bit value from registers `rs2` and `rs2+1` | |||
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| [NOTE] | |||
| ==== | |||
| As the access size is 64-bit, accesses are only considered naturally aligned for effective addresses that are a multiple of 8. In this case, these instruction are guaranteed to not raise an address-misaligned exception. | |||
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| As the access size is 64-bit, accesses are only considered naturally aligned for effective addresses that are a multiple of 8. In this case, these instruction are guaranteed to not raise an address-misaligned exception. | |
| As the access size is 64-bit, accesses are only considered naturally aligned for effective addresses that are a multiple of 8. Only in this case are these instruction guaranteed to not raise an address-misaligned exception. |
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The way you suggest it was the first way I also wrote it, but it is not correct.
If your EEI guarantees that misaligned instructions do not trap but are emulated in hardware, they are also guaranteed not to trap.
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