Add Zfa support (excl. quad-precision instructions) #251
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jrtc27
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May 9, 2023
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jrtc27
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May 11, 2023
jrtc27
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jrtc27
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May 23, 2023
To support the implementation of the Zfa extension in SAIL, this creates the necessary infrastructure (i.e., a file to hold it, and the existence macro), preparing the tree for the Zfa implementation. Signed-off-by: Philipp Tomsich <[email protected]>
FLI.S provides support for loading one of 32 immediate floating-point constants (so it is not really a 'load immediate', but rather a 'load constant') with a single instruction using a 32-entry lookup table. Lacking further guidance in the specification, we disallow this instruction for Xfinx. Signed-off-by: Philipp Tomsich <[email protected]>
FMINM.S and FMAXM.S provide similar functionality to FMIN.S and FMAX.S, differing only in their NaN-handling: * FMIN/FMAX return a canonical NaN only if both operands are a NaN * FMINM/FMAXM return a canonical Nan if any operand is a NaN Consequently, the implementation is identical to FMIN/FMAX with only the NaN-related tests changed. Signed-off-by: Philipp Tomsich <[email protected]>
FLI.H & FLI.D provides support for loading one of 32 immediate floating-point constants(16-bit for FLI.H, 64-bit for FLI.D) with a single instruction using a 32-entry lookup table. Signed-off-by: Charalampos Mitrodimas <[email protected]> Reviewed-by: Philipp Tomsich <[email protected]>
FMINM.D and FMAXM.D provide similar functionality to FMIN.D and FMAX.D, differing only in ther NaN-handling: * FMIN/FMAX return a canonical NaN only if both operands are a NaN * FMINM/FMAXM return a canonical NaN if any operand is a NaN Signed-off-by: Charalampos Mitrodimas <[email protected]> Signed-off-by: Philipp Tomsich <[email protected]> Reviewed-by: Philipp Tomsich <[email protected]>
FMINM.H and FMAXM.H provide similar functionality to FMIN.H and FMAX.H, differing only in ther NaN-handling: * FMIN/FMAX return a canonical NaN only if both operands are a NaN * FMINM/FMAXM return a canonical NaN if any operand is a NaN Signed-off-by: Charalampos Mitrodimas <[email protected]> Signed-off-by: Philipp Tomsich <[email protected]> Reviewed-by: Philipp Tomsich <[email protected]>
…FROUNDNX.D FROUND.H instruction rounds the half-precision floating-point number in floating-point register rs1 and writes that integer, represented as a half-precision floating-point number to floating-point register rd while: * Zero and infinite inputs are copied to rd unmodified. * NaN inputs cause the invalid operation exception flag to be set. Instructions FROUND.S and FROUND.D are analogously defined to operate on single-precision numbers(FROUND.S) and double-precision numbers(FROUND.D) FROUNDNX.H instruction is defined similarly, but also sets the inexact exception flag if the input differs from the rounded result and is not NaN. Instructions FROUNDNX.S and FROUNDNX.D are analogously defined to operate on single-precision numbers(FROUNDNX.S) and double-precision numbers(FROUNDNX.D) Signed-off-by: Charalampos Mitrodimas <[email protected]> Reviewed-by: Philipp Tomsich <[email protected]>
FMVH.X.D instruction is available for RV32 only and moves bits 63:32 of floating-point register rs1 into integer register rd. FMVP.D.X instruction is available for RV32 only and moves a double-precision number from a pair of integer registers into a floating-point register. Integer registers rs1 and rs2 supply bits 31:0 and 63:32, respectively. Signed-off-by: Charalampos Mitrodimas <[email protected]> Reviewed-by: Philipp Tomsich <[email protected]>
FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S instructions, excpet that quiet NaN inputs do not cause the invalid operation exception flag to be set. FLEQ.H and FLTQ.H instructions are analogously defined to operate on half-precision numbers. FLEQ.D and FLTQ.D instructions are analogously defined to operate on double-precision numbers. Signed-off-by: Charalampos Mitrodimas <[email protected]> Reviewed-by: Philipp Tomsich <[email protected]>
The FCVTMOD.W.D instruction is defined similarly to the FCVT.W.D instruction, with the following differences: * FCVTMOD.W.D always rounds towards zero. * Bits 31:0 are taken from the rounded, unbounded two's complement result, then sign-extended to XLEN bits and written to integer register rd. * Positive infinity, negative infinity and NaN are converted to zero. Signed-off-by: Charalampos Mitrodimas <[email protected]> Signed-off-by: Philipp Tomsich <[email protected]> Reviewed-by: Philipp Tomsich <[email protected]>
Signed-off-by: Charalampos Mitrodimas <[email protected]>
This commits also adds the following functions from Softfloat C library into SAIL interface, for using them in the FROUND.[H,S,D] & FROUNDNX.[H,S,D] instructions: * f16_roundToInt * f32_roundToInt * f64_roundToInt Signed-off-by: Charalampos Mitrodimas <[email protected]>
In this commit we are changing the Softfloat functions that we use in fleq.* & fltq.* instructions, these were missing from riscv_softfloat_interface.sail. We are also writing the Floating Point exceptions of the conversion. Signed-off-by: Charalampos Mitrodimas <[email protected]>
Some extensions (all of Zfa, as currently specified) allow operations on non-X registers only... and even if that restriction is eventually lifted, instructions such as fli.s will never be available for in-X. This change adds auto-(un)boxing accessors for F_[HSD] and refactors the F_or_X_[HSD] accessors to use these. Signed-off-by: Philipp Tomsich <[email protected]>
Signed-off-by: Philipp Tomsich <[email protected]>
Don't check for the presence of F, if Zfa is present.
Signed-off-by: Charalampos Mitrodimas <[email protected]>
Detailed:
* SOFTFLOAT_POSTLUDE handles XOR of fflags, no need to use our own
fflags variable.
* If statements (..) removal.
* Make variables that are not mutated, immutable.
* Removal of unnecessary variable.
Signed-off-by: Charalampos Mitrodimas <[email protected]>
Adding the Softfloat functions that were missing in hardwritten_support/0.11/riscv_extras_fdext.lem fixes a compilation issue when not building a specific emulator. Signed-off-by: Charalampos Mitrodimas <[email protected]>
This reverts commit 086e5e5.
The original implementation of fcvtmod.w.d (in fcvtmod_helper) used both an imperative style and suffered from the following shortcomings: - it required extra work (i.e., it first converted to a 64bit value) - the conversion from a normal fixed-point significand to the 64bit value (and the raising of exception flags) was hard to follow (and hard to verify) This rewrites the helper function in a purely functional style and performs the conversion from a fixed-point (53 bit precision) number to a 32 bit integer using a single exponentiation (i.e. a single shift operation). Signed-off-by: Philipp Tomsich <[email protected]> Signed-off-by: Charalampos Mitrodimas <[email protected]>
Add the following style improvements: - capitalize comments - inline fcvtmod_helper_inner - remove parathesis around conditions - fix indentation - remove unnecessary round trips through integers - simplify type annotations
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@jrtc27 If you are happy with this now, please hit 'Approve' and I'll merge it (after squashing some of the history). The copyright header is also missing on this one, but I'd rather clean this up as part of the 'great update of the copyright year and reapplication of the header'. |
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Merging this as-is, as I will move the apply_header change forward in a few minutes. |
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This history is a total mess. It should not have been merged as-is. Moreover, past PRs have been merged with rebase and merge, not an actual merge commit. |
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(Please treat this the same way as you would treat any other open-source project like LLVM, GCC, binutils, etc, i.e. clean linear history) |
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OK to force-push a squash given that it was just a few minutes ago? |
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Almost certainly fine, I doubt anyone's pulled it yet |
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Fixed. I certainly prefer merging things on the command line over the web UI, as I actually see what I am doing there... |
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This adds the (proposed) Zfa (FP gap fillers) instructions, as specified in chapter 25 of https://github.com/riscv/riscv-isa-manual/releases.
Tested against Spike (Zfa is merged in Spike as riscv-software-src/riscv-isa-sim@09140c0) using the (preliminary) ACT support (see pull-request riscv-non-isa/riscv-arch-test#330).