v1.0.2-1 make register field names consistent for c.mul, c.not, c.zext.b

riscvarchive · Feb 3, 2023 · b9e5e3c · b9e5e3c
1 parent 58ef3a8
commit b9e5e3c
Show file tree

Hide file tree

Showing 3 changed files with 5 additions and 5 deletions.
diff --git a/Zc-specification/c_mul.adoc b/Zc-specification/c_mul.adoc
@@ -15,7 +15,7 @@ Encoding (RV32, RV64)::
     { bits:  2, name: 0x1, attr: ['C1'] },
     { bits:  3, name: 'rs2\'', attr: ['SRC2']  },
     { bits:  2, name: 0x2, attr: ['FUNCT2'] },
-    { bits:  3, name: 'rsd\'', attr: ['SRCDST'] },
+    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
     { bits:  3, name: 0x7 },
     { bits:  3, name: 0x4, attr: ['FUNCT3'] },
 ],config:{bits:16}}
@@ -25,7 +25,7 @@ Description::
 This instruction multiplies XLEN bits of the source operands from _rsd'_ and _rs2'_ and writes the lowest XLEN bits of the result to _rsd'_.
 
 [NOTE]
-  _rsd'_ and _rs2'_ are from the standard 8-register set x8-x15.
+  _rd'/rs1'_ and _rs2'_ are from the standard 8-register set x8-x15.
 
 Prerequisites::
 M or Zmmul must be configured.
@@ -35,7 +35,7 @@ M or Zmmul must be configured.
 
 [NOTE]
 
-  The SAIL module variable for _rsd'_ is called _rsdc_, and for _rs2'_ is called _rs2c_.
+  The SAIL module variable for _rd'/rs1'_ is called _rsdc_, and for _rs2'_ is called _rs2c_.
 
 Operation::
 [source,sail]

diff --git a/Zc-specification/c_not.adoc b/Zc-specification/c_not.adoc
@@ -33,7 +33,7 @@ None
 32-bit equivalent::
 [source,sail]
 --
-xori rd, rs, -1
+xori rd'/rs1', rd'/rs1', -1
 --
 
 [NOTE]

diff --git a/Zc-specification/c_zext_b.adoc b/Zc-specification/c_zext_b.adoc
@@ -35,7 +35,7 @@ None
 32-bit equivalent::
 [source,sail]
 --
-andi rsd, rsd, 0xff
+andi rd'/rs1', rd'/rs1', 0xff
 --
 
 [NOTE]