Skip to content

Commit

Permalink
Fix and add unittests.
Browse files Browse the repository at this point in the history
  • Loading branch information
Rot127 committed Mar 16, 2024
1 parent 550b331 commit 0642a01
Show file tree
Hide file tree
Showing 5 changed files with 29 additions and 6 deletions.
2 changes: 1 addition & 1 deletion .github/workflows/black.yaml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
name: black

on: [pull_request]
on: [pull_request, push]

jobs:
linter:
Expand Down
2 changes: 1 addition & 1 deletion .github/workflows/flake8.yml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
name: flake8

on: [pull_request]
on: [pull_request, push]

jobs:
linter:
Expand Down
2 changes: 1 addition & 1 deletion .github/workflows/reuse.yaml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
name: reuse

on: [pull_request]
on: [pull_request, push]

jobs:
linter:
Expand Down
22 changes: 22 additions & 0 deletions .github/workflows/unittests.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
name: Unit Tests

on: [pull_request, push]

jobs:
run:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- name: Set up Python 3.11
uses: actions/setup-python@v3
with:
python-version: '3.11'
- name: Install
run: |
python3 -m pip install --upgrade pip
pip3 install -r requirements.txt
pip3 install .
- name: Run unit tests
run: |
cd Tests
python3 -m unittest discover -s . -t .
7 changes: 4 additions & 3 deletions LLVMImporter.py
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ class LLVMImporter:
sub_instruction_names = list()
sub_instructions = dict()
hardware_regs = dict()
rzil_compiler = None
rzilcompiler = None
edited_files: [str] = list()

def __init__(self, build_json: bool, gen_rzil: bool, skip_pcpp: bool, rzil_compile: bool, test_mode=False):
Expand Down Expand Up @@ -202,7 +202,7 @@ def generate_hexagon_json(self):

def setup_rzil_compiler(self):
log("Init compiler")
self.rzil_compiler = Compiler(ArchEnum.HEXAGON)
self.rzilcompiler = Compiler(ArchEnum.HEXAGON)
if not self.skip_pcpp:
self.rzilcompiler.run_preprocessor()

Expand Down Expand Up @@ -352,7 +352,8 @@ def parse_instructions(self) -> None:
t.n = i
t.postfix = f"Succ. compiled: {compiled_insn}/{len(no_pseudo)}"
t.update()
self.rzilcompiler.transformer.ext.report_missing_fcns()
if self.gen_rzil:
self.rzilcompiler.transformer.ext.report_missing_fcns()

log("Parsed {} normal instructions.".format(len(self.normal_instructions)))
log("Parsed {} sub-instructions.".format(len(self.sub_instructions)))
Expand Down

0 comments on commit 0642a01

Please sign in to comment.