Handle MOD registers in il reg read/write

rizinorg · Nov 11, 2023 · 8f3b134 · 8f3b134
1 parent 1ac2fe8
commit 8f3b134
Showing 1 changed file with 4 additions and 0 deletions.
diff --git a/handwritten/hexagon_il_c/functions.c b/handwritten/hexagon_il_c/functions.c
@@ -420,6 +420,7 @@ static void log_reg_read(RZ_BORROW HexPkt *pkt, ut8 reg_num, HexRegClass reg_cla
 			pkt->il_op_stats.ctr_read |= (1 << (reg_num + 1));
 		}
 		// fallthrough
+	case HEX_REG_CLASS_MOD_REGS:
 	case HEX_REG_CLASS_CTR_REGS:
 		if (tmp_reg) {
 			pkt->il_op_stats.ctr_tmp_read |= (1 << reg_num);
@@ -468,6 +469,7 @@ static void log_reg_write(RZ_BORROW HexInsnPktBundle *bundle, ut8 reg_num, HexRe
 	case HEX_REG_CLASS_CTR_REGS64:
 		pkt->il_op_stats.ctr_written |= (1 << (reg_num + 1));
 		// fallthrough
+	case HEX_REG_CLASS_MOD_REGS:
 	case HEX_REG_CLASS_CTR_REGS:
 		pkt->il_op_stats.ctr_written |= (1 << reg_num);
 		break;
@@ -548,6 +550,7 @@ RZ_IPI RZ_OWN RzILOpEffect *hex_write_reg(RZ_BORROW HexInsnPktBundle *bundle, co
 		high_name = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, reg_num + 1, false, true, true);
 		high_val = SHIFTR0(DUP(val), U8(HEX_GPR_WIDTH));
 		// fallthrough
+	case HEX_REG_CLASS_MOD_REGS:
 	case HEX_REG_CLASS_CTR_REGS:
 		low_name = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, reg_num, false, true, true);
 		low_val = CAST(HEX_GPR_WIDTH, IL_FALSE, val);
@@ -646,6 +649,7 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b
 		}
 		val_width = HEX_GPR64_WIDTH;
 		// fallthrough
+	case HEX_REG_CLASS_MOD_REGS:
 	case HEX_REG_CLASS_CTR_REGS:
 		if ((pkt->il_op_stats.ctr_written & (1 << reg_num)) && (pkt->il_op_stats.ctr_read & (1 << reg_num))) {
 			// If read and writes overlap, return the new register for each read.