Add new cortex-m-interrupt-number crate

Cargo.toml

@@ -4,6 +4,7 @@ members = [
     "cortex-m",
     "cortex-m-rt",
     "cortex-m-semihosting",
+    "cortex-m-interrupt-number",
     "panic-itm",
     "panic-semihosting",
     "testsuite",

cortex-m-interrupt-number/Cargo.toml

@@ -0,0 +1,12 @@
+[package]
+name = "cortex-m-interrupt-number"
+version = "1.0.0"
+edition = "2021"
+categories = ["embedded", "hardware-support", "no-std"]
+description = "Shared trait for Cortex-M interrupt numbers"
+keywords = ["arm", "cortex-m", "register", "peripheral"]
+license = "MIT OR Apache-2.0"
+readme = "README.md"
+repository = "https://github.com/rust-embedded/cortex-m"
+
+[dependencies]

cortex-m-interrupt-number/README.md

@@ -0,0 +1,10 @@
+# cortex-m-interrupt-number
+
+This crate provides the definition of a trait that is shared between
+the `cortex-m` crate and all peripheral access crates (PACs) for
+Cortex-M microcontrollers.
+
+The PACs must implement the `InterruptNumber` trait on an enum of possible
+interrupts; refer to the `InterruptNumber` [documentation] for more details.
+
+[documentation]: https://docs.rs/cortex-m-interrupt-number

cortex-m-interrupt-number/src/lib.rs

@@ -0,0 +1,20 @@
+/// Trait for enums of external interrupt numbers.
+///
+/// This trait should be implemented by a peripheral access crate (PAC)
+/// on its enum of available external interrupts for a specific device.
+/// Each variant must convert to a u16 of its interrupt number,
+/// which is its exception number - 16.
+///
+/// # Safety
+///
+/// This trait must only be implemented on enums of device interrupts. Each
+/// enum variant must represent a distinct value (no duplicates are permitted),
+/// and must always return the same value (do not change at runtime).
+///
+/// These requirements ensure safe nesting of critical sections.
+pub unsafe trait InterruptNumber: Copy {
+    /// Return the interrupt number associated with this variant.
+    ///
+    /// See trait documentation for safety requirements.
+    fn number(self) -> u16;
+}

cortex-m/CHANGELOG.md

@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Breaking changes
 
 - `NVIC::request()` no longer requires `&mut self`.
+- `InterruptNumber` is now provided by the `cortex-m-interrupt-number` trait
 
 ### Added
 - Updated `SCB.ICSR.VECTACTIVE`/`SCB::vect_active()` to be 9 bits instead of 8.

cortex-m/Cargo.toml

@@ -17,6 +17,7 @@ rust-version = "1.59"
 links = "cortex-m"  # prevent multiple versions of this crate to be linked together
 
 [dependencies]
+cortex-m-interrupt-number = "1.0.0"
 critical-section = "1.0.0"
 volatile-register = "0.2.0"
 bitfield = "0.13.2"

cortex-m/src/interrupt.rs

@@ -5,27 +5,6 @@ use core::arch::asm;
 #[cfg(cortex_m)]
 use core::sync::atomic::{compiler_fence, Ordering};
 
-/// Trait for enums of external interrupt numbers.
-///
-/// This trait should be implemented by a peripheral access crate (PAC)
-/// on its enum of available external interrupts for a specific device.
-/// Each variant must convert to a u16 of its interrupt number,
-/// which is its exception number - 16.
-///
-/// # Safety
-///
-/// This trait must only be implemented on enums of device interrupts. Each
-/// enum variant must represent a distinct value (no duplicates are permitted),
-/// and must always return the same value (do not change at runtime).
-///
-/// These requirements ensure safe nesting of critical sections.
-pub unsafe trait InterruptNumber: Copy {
-    /// Return the interrupt number associated with this variant.
-    ///
-    /// See trait documentation for safety requirements.
-    fn number(self) -> u16;
-}
-
 /// Disables all interrupts in the current core.
 #[cfg(cortex_m)]
 #[inline]

cortex-m/src/peripheral/nvic.rs

@@ -4,7 +4,7 @@ use volatile_register::RW;
 #[cfg(not(armv6m))]
 use volatile_register::{RO, WO};
 
-use crate::interrupt::InterruptNumber;
+use cortex_m_interrupt_number::InterruptNumber;
 use crate::peripheral::NVIC;
 
 /// Register block