Skip to content

Actions: rust-embedded/riscv

Actions

Changelog check

Actions

Loading...
Loading

Show workflow options

Create status badge

Loading
changelog.yaml
146 workflow run results
146 workflow run results

Filter by Event

Filter by Status

Filter by Branch

Filter by Actor

riscv: build: make cfg variables more robust Changelog check #170: Pull request #205 synchronize by rmsyn
May 5, 2024 21:26 15s rmsyn:build/robust-cfg
rmsyn:build/robust-cfg
May 5, 2024 21:26 15s
riscv: build: make cfg variables more robust Changelog check #169: Pull request #205 synchronize by rmsyn
May 5, 2024 21:18 18s rmsyn:build/robust-cfg
rmsyn:build/robust-cfg
May 5, 2024 21:18 18s
riscv: build: make cfg variables more robust Changelog check #168: Pull request #205 synchronize by rmsyn
May 5, 2024 21:00 16s rmsyn:build/robust-cfg
rmsyn:build/robust-cfg
May 5, 2024 21:00 16s
riscv: register: fix target architecture conditional compilation Changelog check #167: Pull request #204 labeled by romancardenas
May 5, 2024 15:07 12s rmsyn:fixup/riscv/macro-conditional-comp
rmsyn:fixup/riscv/macro-conditional-comp
May 5, 2024 15:07 12s
riscv: build: make cfg variables more robust Changelog check #166: Pull request #205 synchronize by rmsyn
May 5, 2024 04:56 15s rmsyn:build/robust-cfg
rmsyn:build/robust-cfg
May 5, 2024 04:56 15s
riscv: register: fix target architecture conditional compilation Changelog check #165: Pull request #204 synchronize by rmsyn
May 5, 2024 04:48 21s rmsyn:fixup/riscv/macro-conditional-comp
rmsyn:fixup/riscv/macro-conditional-comp
May 5, 2024 04:48 21s
riscv: build: make cfg variables more robust Changelog check #164: Pull request #205 synchronize by rmsyn
May 5, 2024 04:17 19s rmsyn:build/robust-cfg
rmsyn:build/robust-cfg
May 5, 2024 04:17 19s
riscv: build: make cfg variables more robust Changelog check #163: Pull request #205 synchronize by rmsyn
May 4, 2024 21:17 2m 18s rmsyn:build/robust-cfg
rmsyn:build/robust-cfg
May 4, 2024 21:17 2m 18s
riscv: build: make cfg variables more robust Changelog check #162: Pull request #205 opened by rmsyn
May 4, 2024 21:15 20s rmsyn:build/robust-cfg
rmsyn:build/robust-cfg
May 4, 2024 21:15 20s
riscv-rt: Support for vectored mode interrupt handling Changelog check #161: Pull request #200 synchronize by romancardenas
May 4, 2024 16:34 4m 1s vectored-rt
vectored-rt
May 4, 2024 16:34 4m 1s
riscv-rt: Support for vectored mode interrupt handling Changelog check #160: Pull request #200 synchronize by romancardenas
May 4, 2024 16:33 2m 22s vectored-rt
vectored-rt
May 4, 2024 16:33 2m 22s
riscv-rt: Support for vectored mode interrupt handling Changelog check #159: Pull request #200 ready_for_review by romancardenas
May 4, 2024 16:09 13s vectored-rt
vectored-rt
May 4, 2024 16:09 13s
riscv-rt: Support for vectored mode interrupt handling Changelog check #158: Pull request #200 unlabeled by romancardenas
May 4, 2024 16:08 15s vectored-rt
vectored-rt
May 4, 2024 16:08 15s
riscv-rt: Support for vectored mode interrupt handling Changelog check #157: Pull request #200 synchronize by romancardenas
May 4, 2024 15:55 2m 42s vectored-rt
vectored-rt
May 4, 2024 15:55 2m 42s
riscv: register: fix target architecture conditional compilation Changelog check #156: Pull request #204 synchronize by rmsyn
May 3, 2024 21:36 20s rmsyn:fixup/riscv/macro-conditional-comp
rmsyn:fixup/riscv/macro-conditional-comp
May 3, 2024 21:36 20s
riscv: register: fix target architecture conditional compilation Changelog check #155: Pull request #204 synchronize by rmsyn
May 3, 2024 20:55 3m 4s rmsyn:fixup/riscv/macro-conditional-comp
rmsyn:fixup/riscv/macro-conditional-comp
May 3, 2024 20:55 3m 4s
riscv: register: fix target architecture conditional compilation Changelog check #154: Pull request #204 synchronize by rmsyn
May 3, 2024 00:27 51s rmsyn:fixup/riscv/macro-conditional-comp
rmsyn:fixup/riscv/macro-conditional-comp
May 3, 2024 00:27 51s
riscv: register: fix target architecture conditional compilation Changelog check #153: Pull request #204 opened by rmsyn
May 3, 2024 00:24 21s rmsyn:fixup/riscv/macro-conditional-comp
rmsyn:fixup/riscv/macro-conditional-comp
May 3, 2024 00:24 21s
Changelog check Changelog check #152: Merge group checks requested
May 2, 2024 13:32 16s
May 2, 2024 13:32 16s
riscv: register: exports macros for custom CSRs Changelog check #151: Pull request #203 synchronize by rmsyn
May 1, 2024 04:12 3m 4s rmsyn:register/export-macros
rmsyn:register/export-macros
May 1, 2024 04:12 3m 4s
riscv: register: exports macros for custom CSRs Changelog check #150: Pull request #203 synchronize by rmsyn
May 1, 2024 02:16 2m 46s rmsyn:register/export-macros
rmsyn:register/export-macros
May 1, 2024 02:16 2m 46s
riscv: register: exports macros for custom CSRs Changelog check #149: Pull request #203 opened by rmsyn
May 1, 2024 02:14 18s rmsyn:register/export-macros
rmsyn:register/export-macros
May 1, 2024 02:14 18s
Changelog check Changelog check #147: Merge group checks requested
April 22, 2024 10:01 39s
April 22, 2024 10:01 39s
Add Mstatus::from(usize) Changelog check #146: Pull request #201 opened by jasonwhite
April 19, 2024 21:30 1m 3s jasonwhite:jw/mstatus-from-bits
jasonwhite:jw/mstatus-from-bits
April 19, 2024 21:30 1m 3s
riscv-rt: Support for vectored mode interrupt handling Changelog check #145: Pull request #200 synchronize by romancardenas
April 12, 2024 16:55 2m 0s vectored-rt
vectored-rt
April 12, 2024 16:55 2m 0s