Actions: rust-embedded/riscv
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1,139 workflow run results
1,139 workflow run results
cfg
variables more robust
Build check (riscv)
#177:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Build check (riscv-peripheral)
#90:
Pull request #205
synchronize
by
rmsyn
riscv
: register: fix target architecture conditional compilation
Changelog check
#167:
Pull request #204
labeled
by
romancardenas
riscv
: register: fix target architecture conditional compilation
Check Labels
#125:
Pull request #204
labeled
by
romancardenas
cfg
variables more robust
Build check (riscv)
#176:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Build check (riscv-peripheral)
#89:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Lints compliance check
#280:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Build check (riscv-rt)
#187:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Changelog check
#166:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Check Labels
#124:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Code formatting check
#456:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Build check (riscv-semihosting)
#117:
Pull request #205
synchronize
by
rmsyn
riscv
: register: fix target architecture conditional compilation
Changelog check
#165:
Pull request #204
synchronize
by
rmsyn
riscv
: register: fix target architecture conditional compilation
Code formatting check
#455:
Pull request #204
synchronize
by
rmsyn
riscv
: register: fix target architecture conditional compilation
Check Labels
#123:
Pull request #204
synchronize
by
rmsyn
riscv
: register: fix target architecture conditional compilation
Build check (riscv-peripheral)
#88:
Pull request #204
synchronize
by
rmsyn
riscv
: register: fix target architecture conditional compilation
Lints compliance check
#279:
Pull request #204
synchronize
by
rmsyn
riscv
: register: fix target architecture conditional compilation
Build check (riscv)
#175:
Pull request #204
synchronize
by
rmsyn
riscv
: register: fix target architecture conditional compilation
Build check (riscv-semihosting)
#116:
Pull request #204
synchronize
by
rmsyn
riscv
: register: fix target architecture conditional compilation
Build check (riscv-rt)
#186:
Pull request #204
synchronize
by
rmsyn
cfg
variables more robust
Code formatting check
#454:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Changelog check
#164:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Check Labels
#122:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Build check (riscv-rt)
#185:
Pull request #205
synchronize
by
rmsyn
cfg
variables more robust
Lints compliance check
#278:
Pull request #205
synchronize
by
rmsyn